Design & Reuse
4833 IP
3101
0.0
Simulation VIP for UCIE
Best-in-class UCIe Verification IP for your IP, SoC, and system-level design testing....
3102
0.0
Simulation VIP for UCIE
Best-in-Class UCIe Verification IP for your IP, SoC, and System-Level Design Testing The Cadence Verification IP (VIP) for Universal Chiplet Interconn...
3103
0.0
Simulation VIP for UFS
In production since 2012 on multiple production designs....
3104
0.0
Simulation VIP for USB
The Cadence® Verification IP (VIP) for USB is a complete VIP solution for the Universal Serial Bus Revision 3.2 Specification and errata. It provides ...
3105
0.0
Simulation VIP for USB4
Used by all top market leaders semiconductor companies....
3106
0.0
Simulation VIP for xSPI
xSPI in production since 2019 for many production designs....
3107
0.0
Single Channel HDLC Controller
Inicore's iniHDLC family of High-Level Data Link Controller (HDLC) cores consist of a Receiver (FPR: From Primary Rate) and a Transmitter (TPR: To Pri...
3108
0.0
PipelineZero 32-bit Embedded Processor
The BA20 is a small, ultra-low-power, and very efficient 32-bit processor. It is an excellent step up from the 8051 and other 8- and 16-bit microcontr...
3109
0.0
MIPI C-PHY 2.1 TX/RX, 6nm
InPsytech proudly presents our groundbreaking innovation, the MIPI C-PHY Ver2.1 IP, setting new standards in connectivity solutions. Designed to empow...
3110
0.0
MIPI C-PHY CSI-2 TX+ (Transmitter) IP in TSMC 40ULP
The MXL-CPHY-2p5G-CSI-2-TX+-T-40ULP is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY is configured as a MIPI Maste...
3111
0.0
MIPI C-PHY DSI RX (Transmitter/Host) IP in TSMC 22ULL
The MXL-CPHY-2p5G-DSI-RX-T-22ULL is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificati...
3112
0.0
MIPI C-PHY v1.2 D-PHY v2.1 RX 3 trios/4 Lanes in GlobalFoundries (12nm) for Automotive
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
3113
0.0
MIPI C-PHY v1.2 D-PHY v2.1 RX 3 trios/4 Lanes in Samsung (SF2P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
3114
0.0
MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes for TSMC 12FFCP
Synopsys’ integrated DesignWare C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and...
3115
0.0
MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in GlobalFoundries (12nm) for Automotive
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
3116
0.0
MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in Samsung (SF2P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
3117
0.0
MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in Samsung (SF5A, SF4A) for Automotive
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
3118
0.0
MIPI C-PHY v2.0 D-PHY v2.1 for TSMC N5A
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
3119
0.0
MIPI C-PHY v2.0 D-PHY v2.1 RX 3 trios/4 Lanes in Samsung (SF2A, SF4A) for Automotive
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
3120
0.0
MIPI C-PHY v2.0 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (N7, N5A, N3A)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
3121
0.0
MIPI C-PHY v2.0 D-PHY v2.1 RX for GF 12LP+
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
3122
0.0
MIPI C-PHY v2.0 D-PHY v2.1 RX for TSMC N6
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
3123
0.0
MIPI C-PHY v2.0 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (N7) for Automotive
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
3124
0.0
MIPI C-PHY v2.0 D-PHY v2.1 TX 3 trios/4 Lanes in Samsung (SF5A, SF4A) for Automotive
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
3125
0.0
MIPI C-PHY v2.0 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (N7)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
3126
0.0
MIPI C-PHY v2.0 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (N7, N6, N6C)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
3127
0.0
MIPI C-PHY/D-PHY Combo CSI-2 TX (Transmitter) in TSMC 40ULP
The MXL-CDPHY-CSI-2-TX-T-40ULP is a high-frequency, low-power, low-cost, source-synchronous, physical layer supporting the MIPI Alliance Specification...
3128
0.0
MIPI C-PHY/D-PHY Combo CSI-2 TX (Transmitter) IP in TSMC 65LP
The MXL-CDPHY-CSI-2-TX-T-65LP is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY is configured as a MIPI Master supp...
3129
0.0
MIPI C-PHY/D-PHY Combo CSI-2 TX 3.5Gsps/trio in TSMC 28nm
The MXL-CDPHY-3p5G-CSI-2-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specifi...
3130
0.0
MIPI C-PHY/D-PHY Combo CSI-2 TX 4.5Gsps/trio in TSMC 28nm
The MXL-CDPHY-4p5G-CSI-2-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specifi...
3131
0.0
MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 3.5Gsps/2.5Gbps, 2T/2L
The MXL-CDPHY-CSI-2-TX+-40LP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification f...
3132
0.0
MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP in TSMC 40ULP
The MXL-CDPHY-CSI-2-TX+-40ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification ...
3133
0.0
MIPI C-PHY/D-PHY Combo DSI RX (Receiver) IP in TSMC 28HPC+
The MXL-CDPHY-DSI-RX-T-28HPC+ is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY is configured as MIPI Slave support...
3134
0.0
MIPI C-PHY/D-PHY Combo DSI TX (Transmitter) IP in TSMC 55G
The MXL-CDPHY-DSI-TX-T-55G is a high-frequency low-power, high-performance, physical Layer. The PHY is configured as a MIPI Master supporting display ...
3135
0.0
MIPI C-PHY/D-PHY Combo Universal IP in UMC 40LP
The MXL-CDPHY-UNIV-U-40LP is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY can be configured as a MIPI Master or M...
3136
0.0
MIPI C/D COMBO RX HS PHY UMC 28/22nm
Our silicon-proven MIPI C- and D-PHY combo Rx PHY is compliant with Camera Serial Interface (CSI) version 1.2, supporting D-PHY speeds up to 4.5 GHz (...
3137
0.0
MIPI C/D COMBO TX HS PHY UMC 28/22nm
The MIPI C/D combo PHY Tx IP is compliant with the Display Serial Interface (DSI) with D-PHY signaling up to 4.5GHz and C-PHY operating at a symbol ra...
3138
0.0
MIPI C/D COMBO TX PHY, 5nm
The MIPI C/D combo PHY Tx IP is compliant with the Display Serial Interface (DSI) with D-PHY signaling up to 4.5GHz and C-PHY operating at a symbol ra...
3139
0.0
MIPI CSI-2 Receiver
The Arasan CSI-2 Receiver IP Core functions as a MIPI Camera Serial Interface (CSI-2 Combo) Receiver, which interfaces between a peripheral device (Ca...
3140
0.0
MIPI D-PHY UMC 40LL
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
3141
0.0
MIPI D-PHY 1.2 TX/RX, 22nm
The MIPI D-PHY Tx IP is compliant with the Display Serial Interface (DSI) with D-PHY signaling up to 2.5GHz. This IP is designed for extreme low power...
3142
0.0
MIPI D-PHY 2-Lane CSI-2 TX (Transmitter) in TowerJazz 65nm
The MXL-DPHY-CSI-2-TX-2L-TW-65ISC is a high-frequency low-power, low-cost, source synchronous, Physical Layer supporting the MIPI Alliance Standard fo...
3143
0.0
MIPI D-PHY 4 Lane CSI-2 TX (Transmitter) in TowerJazz 110nm
The MXL-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The...
3144
0.0
MIPI D-PHY 4-Lane CSI2-TX (Transmitter) in TowerJazz 65nm
The MXL-DPHY-0p2G-CSI-2-TX-T-180BCD is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard ...
3145
0.0
MIPI D-PHY CSI-2 RX (Receiver) in Samsung 28FDSOI
The MXL-DPHY-CSI-2-RX-SS-28FDSOI is a high- frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI® Alliance Standard f...
3146
0.0
MIPI D-PHY CSI-2 RX (Receiver) in TSMC 16FFC
he MXL-DPHY-CSI-2-RX-T-16FFC is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification f...
3147
0.0
MIPI D-PHY CSI-2 RX (Receiver) in TSMC 28HPC+
The MXL-DPHY-CSI-2-RX-T-28HPC+ is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification ...
3148
0.0
MIPI D-PHY CSI-2 RX (Receiver) in TSMC 40LP
The MXL-DPHY-CSI-2-RX-T-40LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for...
3149
0.0
MIPI D-PHY CSI-2 RX (Receiver) in TSMC 65LP
The MXL-DPHY-CSI-2-RX-T-65LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-P...
3150
0.0
MIPI D-PHY CSI-2 RX (Receiver) IP
The MXL-PHY-CSI-2-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. ...