Design & Reuse
1294 IP
51
6.0
2-ch 16-bit stereo Audio ADC
...
52
6.0
2-ch 24-bit 192KSPS Audio DAC
...
53
6.0
2-ch 24-bit 192KSPS Audio DAC
...
54
6.0
2-ch 24-bit 192KSPS Audio DAC; TSMC 40nm LP
...
55
6.0
10-bit dual-port 30MHz ~ 85MHz LVDS Tx;
...
56
6.0
10/100 Base-TX Fast Ethernet PHY; SMIC 40nm LL
SP-10_100_Ethernet-S40LL is a single-port DSP-based Fast Ethernet Transceiver. It contains all the active circuitry required to convert data stream to...
57
6.0
10/100 Base-TX Fast Ethernet PHY; TSMC 55nm GP
...
58
6.0
10/100 Ethernet PHY for TSMC 22nm ULP
10 100ETHERNET-T22ULP18 is a single-port DSP-based Fast Ethernet Transceiver. It contains all the ac?tive circuitry required to convert data stream to...
59
6.0
10/100 Ethernet PHY, TSMC 28nm HPC+
-10 100ETHERNET-T28HPCP18 is a single-port DSP-based Fast Ethernet Transceiver. It contains all the ac?tive circuitry required to convert data stream ...
60
6.0
24-bit 192KSPS Audio DAC
...
61
6.0
24-bit 192KSPS Audio DAC;
...
62
6.0
16-bit 48KSPS stereo Audio ADC
...
63
6.0
16-bit 48KSPS stereo Audio ADC;
...
64
6.0
Camera Demosaicing IP - DAISY (RCCC)
The demosaicing is a color filter interpolation method, and refers to an image processing algorithm for restoring full color values of all pixels in a...
65
6.0
Camera Demosaicing IP - LOTUS (RCCB)
The demosaicing is a color filter interpolation method, and refers to an image processing algorithm for restoring full color values of all pixels in a...
66
6.0
Camera Demosaicing IP - ROSE (RGB-IR)
The demosaicing is a color filter interpolation method, and refers to an image processing algorithm for restoring full color values of all pixels in a...
67
6.0
RapidIO PHY
RapidIO is a high performance, low pin count, packet switched, full duplex, system level interconnect architecture. The architecture addresses the nee...
68
6.0
Single port 10/100 Fast Ethernet Transceiver - TSMC12nm FFC
SP-10 100ETHERNET-T12FFC is a single-port DSP-based Fast Ethernet Transceiver. It contains all the active circuitry required to convert data stream t...
69
6.0
MIPI D-PHY Receiver with PPI
SP_MIPI_DPHY_RX_PPI _T28HPCP is a MIPI D-PHY Receiver, which complies with MIPI D-PHY specification version 1.2. This D-PHY design receives data from ...
70
6.0
MIPI Rx D-PHY
...
71
6.0
USB 2.0 PHY; SMIC 40nm LL
...
72
6.0
USB 2.0 PHY; SMIC 55nm LL
...
73
6.0
USB 3.0 Device
A USB 3.0 Device IP Core that provides high performance SuperSpeed USB connectivity in a small footprint solution for quick and easy implementation of...
74
6.0
LVDS 10 bits dual port transmitter
...
75
5.0
H.264/AVC 1080 60p Baseline Profile Decoder
TMC's TM21745 is a decoder IP core that is compliant with ISO/IEC 14496-10 | ITU-T Rec.H.264. Using TMC's original computer algorithm, we have real...
76
5.0
H.264/AVC 1080 60p Baseline Profile Encoder
- TMC's TM21745 is an encoder IP core that is compliant with ISO/IEC 14496-10 | ITU-T Rec.H.264. - Using TMC's original computer algorithm, we have...
77
5.0
H.264/AVC 4K 60p High Profile Decoder
- TMC's H.264 core (RTL- IP) is designed to be compliant with the H.264 4K Video, which is a highly efficient image compression method standardized in...
78
5.0
H.264/AVC 4K 60p High Profile Encoder
- TMC's H.264 core (RTL- IP) is designed to be compliant with the H.264 4K Video, which is a highly efficient image compression method standardized in...
79
5.0
H.265/HEVC 422 10bit Decoder for 4K
DMNA realizes real time Encoding of 4K (3840 x 2160) and 8K (7680 x 4320) / 60fps video stream compliant with H.265 / HEVC...
80
5.0
H.265/HEVC 422 10bit Encoder for 4K
DMNA realizes real time Encoding of 4K (3840 x 2160) and 8K (7680 x 4320) / 60fps video stream compliant with H.265 / HEVC...
81
5.0
H.265/HEVC H.264/AVC 422 12bit Multi-Codec for 8K
TMC’s HEVC/AVC Multi-Codec IP Core for 4K/8K are designed to be compliant with the H.264 4K (4096 x 2160) Video and H.265 8K (8192 x 4320) Vid...
82
5.0
1:2 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
83
5.0
1:2 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
84
5.0
1:3 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
85
5.0
1:3 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
86
5.0
1:3 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
87
5.0
1:4 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
88
5.0
1:4 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
89
5.0
1:6 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
90
5.0
1:6 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...
91
5.0
SAS 4 Port 12G Recorder
The SAS Recorder IP Core provides an ready to use solution for high speed data recording applications. Simple interface guarantees fast time to marke...
92
5.0
SAS Initiator, 12G, 4 Ports, 48 Gbps, SATA Host
The SAS Initiator Controller IP Core provides an interface to high-speed serial link replacement for the parallel SCSI attachment of mass storage devi...
93
5.0
SATA Device IP Core (1.5, 3.0, 6.0 Gbps)
The Serial ATA Device Controller IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage ...
94
5.0
SATA/SAS 3.0 PHY
With sophisticated architecture and advanced technology, KNiulink SATA/SAS transceiver IP with PMA and PCS layer is designed for low power and high pe...
95
5.0
DDI Color Enhancement (CLREN) IP
BTREE's Color Enhancement IP modifies or emphasizes color by controlling Saturation/Luminance/Hue. BTREE's Color Enhancement can only adjust the color...
96
5.0
DDI High Dynamic Range IP
HDR improves the visibility of the output image compared to the input images by increasing the contrast of the image/video reproduced on the display. ...
97
5.0
DDR3/4 and LPDDR2/3/4/4x Combo PHY&MAC
With sophisticated architecture and advanced technology, this DDR3/4 and LPDDR2/3/4/4x IP combo solution with high performance and low power. In 12~28...
98
5.0
Serial ATA Host Controller (1.5, 3.0, 6.0 Gb/s)
The Serial ATA Host IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices. The ...
99
5.0
Serial ATA Host Controller (1.5, 3.0, 6.0 Gb/s) for Xilinx UltraScale
The Serial ATA Host IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices. The ...
100
5.0
Visually LossLess compression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS)
TMC’s JPEG XS encoder / decoder IP is Visually LossLess compression / decompression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS). T...