Design & Reuse
5577 IP
1651
3.0
P1619/802.1ae (MACSec) GCM/XEX/XTS-AES Core
General Description LAN security standard IEEE 802.1ae (MACSec) uses AES cipher in the GCM mode, while the disk/tape encryption standard IEEE P1619 us...
1652
3.0
32-512 Point Streaming FFT
The FFT1-32-512/4 core implements 32, 64, 128, 256, and 512 point FFT and IFFT in hardware that runs at the clock frequency four times higher than the...
1653
3.0
32/64/128/256/512/1024/2048/4096 Point FFT Core
The FFT4096 core the FFT and IFFT computations for N input samples, where N can be any power of 2 between 32 and 4096 (32, 64, 128,...…4096), in hardw...
1654
3.0
64 POINT FFT
The FFT0064 core implements 64 point FFT in hardware. FFT 64 works on blocks of 64 complex data samples....
1655
3.0
66/2112 Codec for Cyclic Code (2112,2080)
The CEC1-66/2112 core implements the codec for the Forward Error Correction (FEC) cyclic code (2112,2080) used in the IEEE 802.3ap (10G Backplane Ethe...
1656
3.0
Kasumi Encryption Core
The KSM1 core implements Kasumi encryption in compliance with the ETSI SAGE specification. It processes 64-bit blocks using 128-bit key. Basic core is...
1657
3.0
Fault Injection Studio
FortifyIQ’s Fault Injection Studio enables engineers to evaluate and strengthen hardware designs against fault injection attacks, e.g., DFA, SIFA, and...
1658
3.0
MBOA MAC AES Core
Implementation of the new WPAN security standard for MBOA MAC requires the NIST standard AES cipher in CTR and CBC modes (a.k.a. CCM) for encryption ...
1659
3.0
RC4 Keystream Generator
The RC4 core implements the RC4 stream cipher in compliance with the ARC4 specification. It produces the keystream that consists of 8-bit words using ...
1660
3.0
Scalable RSA and Elliptic Curve Accelerator
Rivest-Shamir-Adelman (RSA) is a public-key cryptographic technology that uses the mathematics of so called “finite field exponentiation”. The operati...
1661
3.0
HDCP 2.0 Encryption Suite
HDCP Suite consists of hardware and software components implementing the HDCP 2.0 protocol. The hardware components are fully synchronous and availab...
1662
3.0
PDM to PCM Conversion, SMIC 65nmLL
The AR36S01 is a soft macro low-power digital microphone interface modulator IP. The IP converts stereo/mono 1-bit pulse-density modulated (PDM) bit s...
1663
3.0
IEEE 802.11 WAPI Encryption Core
Implementation of the new Chinese security standard (WAPI) requires running the SMS4 cipher in the WPI mode for encryption and message authentication....
1664
3.0
IEEE 802.15.4 (ZigBee) CCM* AES Cores
IEEE 802.15.4 is the low-power wireless standard that is used by ZigBee Alliance as a base of its ZigBee™ specification. The security design of IEEE 8...
1665
3.0
IEEE 802.16e (WiMAX) AES Core
Implementation of the new WLAN security standard (802.16e) requires the NIST standard AES cipher in CTR and CBC modes (a.k.a. CCM) for encryption and ...
1666
3.0
IEEE 802.1ae (MACsec) 100G Security Processor with Avalon-ST Interface
Implementation of the new LAN security standard IEEE 802.1ae (MACsec) requires the NIST standard AES cipher in the GCM mode for encryption and message...
1667
3.0
IEEE 802.1ae (MACsec) Security Processor
Implementation of the new LAN security standard IEEE 802.1ae (MACsec) requires the NIST standard AES cipher in the GCM mode for encryption and message...
1668
3.0
Generic CCM AES Core
The CCM1 cores are tuned for mid-performance generic AES-CCM applications per NIST SP 800-38C. Specific protocol implementations are available in inte...
1669
3.0
Generic CCM AES Core with CMAC Option
The CCM2 cores are tuned for mid-performance generic AES-CCM applications per NIST SP 800-38C. CCM2 core uses flow-trough design with dedicated input...
1670
3.0
SHA1, SHA2 Cryptographic Hash Cores
The SHA cores provide implementation of cryptographic hashes SHA-1 (core SHA1), SHA-2 (cores SHA2-256 and SHA2-512). The cores utilize “flow-through”...
1671
3.0
UHS-II PHY for SD4/SD5 TSMC 12nm FF
SD 4.0 (UHS-II) achieves a peak interface speed of 3.12 Gbps. Arasan’s UHS-II PHY is compliant with the specification of UHS-II and is an extremely ar...
1672
3.0
UHS-II PHY for SD4/SD5 TSMC 16nm FF
SD 4.0 (UHS-II) achieves a peak interface speed of 3.12 Gbps. Arasan’s UHS-II PHY is compliant with the specification of UHS-II and is an extremely ar...
1673
3.0
Side Channel Studio
FortifyIQ's FortifEDA Side-Channel Studio Analyzes leakage vulnerabilities throughout design flow by generating simulated power traces, performing st...
1674
3.0
High-Performance Lossless Compression Core
Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from the compressed data. ...
1675
3.0
High-Performance Lossless Compression/Encryption Combo Core
Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from the compressed data. ...
1676
3.0
MIPI D-PHY NEC 90nm
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
1677
3.0
MIPI M-PHY Designed For GF 28nm
ACS-AIP-MPHY-28HK MIPI Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A ...
1678
3.0
NIST AES Key Wrap/Unwrap Core
AKW1 implements the NIST standard AES key wrap and unwrap. Core contains the base AES core AES1 and is available for immediate licensing. The design ...
1679
3.0
Elliptic Curve Point Multiply and Verify Core
Elliptic Curve Cryptography (ECC) is a public-key cryptographic technology that uses the mathematics of so called “elliptic curves” and it is a part o...
1680
3.0
Ultra-Compact 3GPP Cipher Core
The ZUC1 core implements ZUC stream cipher in compliance with the 3GPP Confidentiality and Integrity Algorithms 128-EEA3 & 128-EIA3 version 1.6. It pr...
1681
3.0
Ultra-Compact Advanced Encryption Standard (AES, FIPS-197) Core
The AES core implements Rijndael cipher encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit data bloc...
1682
3.0
Ultra-Compact Data Encryption Standard (DES/3DES) Core
The DES1 ASIC/FPGA core is an implementation of the DES and triple DES encryption and decryption in compliance with the NIST Data Encryption Standard....
1683
3.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPM-EW
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
1684
3.0
SNOW 3G Encryption Core
The SNOW3G1 core implements SNOW 3G stream cipher in compliance with the ETSI SAGE specification version 1.1. It produces the keystream that consists ...
1685
3.0
FortifyIQ High-Performance Hybrid Classical and Post-Quantum High-assurance (SCA/DPA/FIA resistant) Cryptography IP Core (ECC/RSA, ML-KEM, ML-DSA)
FortifyIQ’s High-Performance Hybrid Cryptography IP core delivers accelerated support for both classical (RSA, ECC) and post-quantum (ML-KEM, ML-DSA) ...
1686
3.0
FortifyIQ HMAC-SHA256 Secure Core: Hardware Accelerator for SHA-2 and HMAC with Low Latency SCA/FI Protection
FortifyIQ’s SHA-2/HMAC IP core delivers high-speed, hardware-accelerated SHA-2-224/256 hashing and HMAC computation, optimized for secure embedded sys...
1687
3.0
FortifyIQ Hybrid Classical and Post-Quantum High-assurance (SCA/DPA/FIA resistant) Cryptography IP Core (ECC/RSA, ML-KEM, ML-DSA)
FortifyIQ’s Hybrid Cryptography IP core combines traditional asymmetric algorithms, such as RSA and ECC, with post-quantum standards including ML-KEM ...
1688
3.0
FortifyIQ's Compact DPA and FIA Hardened Post-Quantum ML-KEM IP Core for Resource-Constrained Devices (SCA/DPA/FIA resistant)
As quantum computing threatens traditional public-key cryptography, resource-constrained devices must adopt quantum-resistant algorithms without compr...
1689
3.0
FortifyIQ's Compact Post-Quantum ML-DSA Secure Cryptographic Signature IP Core for Resource-Constrained Devices (SCA/DPA/FIA resistant)
As digital signature algorithms face obsolescence in the quantum era, embedded systems require quantum-resistant alternatives that balance performance...
1690
3.0
True Random and Pseudorandom Number Generator
The true random generator core implements true random number generation. The core passes the American NIST Special Publication 800-22 and Diehard Rand...
1691
3.0
LRW-AES Core
LRW3 implements the NIST standard AES cipher in the LRW mode for encryption and decryption. The LRW3 family of cores covers a wide range of area / thr...
1692
3.0
LRW-AES Core
Implementation of the older drafts standard IEEE P1619 required the NIST standard AES cipher in the LRW mode for encryption (AES-LRW). Note that the n...
1693
3.0
LRW-AES Core
Implementation of the new encrypted shared storage media standard IEEE P1619 with AES cipher in the LRW mode....
1694
3.0
Cryptographically Secure Pseudo Random number Generator IP Core
The PRNG1 core implements a cryptographically secure pseudo-random number generator per NIST publication SP800-90. Basic core is small (6,500 gates)...
1695
3.0
RSA Public Key Exponentiation Accelerator
Rivest-Shamir-Adelman (RSA) is a public-key cryptographic technology that uses the mathematics of so called “finite field exponentiation”. The opera...
1696
3.0
USB 3.0 Device
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1697
3.0
SSL/TLS Processor IP Core with an AXI Bus Interface
The SSL1 core implements SSL and/or TLS frameworks with a configurable variety of cipher suites. SSL1-AXI has a “lookaside” interface to the rest of...
1698
3.0
XTS-AES IEEE P1619 Core Families
XTS2 and XTS3 (formerly known as XEX2 and XEX3) implement the NIST standard AES cipher in the XEX/XTS mode for encryption and decryption. The XTS3 fa...
1699
2.0
40-450MHz Programmable Clock Generator PLL, SMIC0.13um
The AR530S13 is a low power programmable phase locked loop (PLL) featured with wide output frequency range from 50MHz to 450MHz. The PLL synchronizes ...
1700
2.0
100~450MHz DDR DLL with 80 Phase Selection, SMIC0.1.3um
The AR531S13 is a low-jitter low power dual channel delay locked loop (DLL) design support for DDR application. It is featured with a wide output freq...