Design & Reuse
1480 IP
951
10.0
Ethernet TSN Switch IP Core - Efficient and Massively Customizable
Packet Architects offers a series of high speed switching/routing IP cores developed using the unique FlexSwitch tool-chain. This allows us to provide...
952
10.0
NTP Server core
NetTimeLogic’s NTP Server is a full hardware (FPGA) only implementation of a SNTPv4 Server according to RFC 4330/5905. It supports hardware timestampi...
953
10.0
Multi Protocol Endpoint IP Core for Safe and Secure Ethernet Network
"The CetraC EndSystem IP coreis the ideal solution to link your Avionic Computer System to a safe & secure embedded network as ARINC664p7, TSN or Safe...
954
10.0
Multi Protocol IO Concentrator (RDC) IP Core for Safe and Secure Ethernet Network
Our IP Core is the ideal solution to link all your equipment, sensor or actuator whatever the used protocol to an Avionic network in a safe & secure m...
955
10.0
DVB-S2 Modulator IP Core
DVBS2_TX.vhd is the transmitter top level component. Inputs consist of one or several streams (transport, generic). The output is a DDR complex baseba...
956
10.0
DVB-S2X Demodulator ASIC silicon proven IP Core
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957
9.0
MIL-STD-1553 IP core
MIL-STD-1553B IP Core implements MIL-STD?1553B standard and provides single or multi?functional interface between host processor and MIL-STD-1553 bus ...
958
9.0
ARINC664 End System IP Core
ARINC664 End System IP is an IP Core that implements ARINC664 part 7 and provides interface between aircraft LRUs and ARINC664 network. As an implemen...
959
8.0
HASH Core, providing MD5, SHA1 and SHA256. Includes DMA and AXI Interface
This is a high performance, small footprint HASH IP Core. It supports three HASH algorithms: MD5, SHA1, SHA256. A S/G DMA engine keeps the core runni...
960
8.0
2D/3D OpenGL ES 2.0 vector graphics IP core - D/AVE NX
D/AVE NX is the latest and most powerful addition to the D/AVE family of rendering cores. It is the first IP to bring 2D and 3D OpenGL ES 2.0 vector g...
961
8.0
Smart Card Reader Controller Core
Implements an interface and controller for communicating between smart cards and host systems using a variety of standard system interfaces. The SCR ...
962
8.0
FortifyIQ's Secure Hybrid Crypto Box IP Core with Classical and Post-Quantum Cryptography for Embedded Systems (AES, HMAC-SHA2, ECC/RSA etc., PQC) (SCA,DPA,FIA secure)
FortifyIQ’s Hybrid Crypto Box IP core is a comprehensive, high-efficiency cryptographic solution that combines RSA, ECC, AES, and SHA-2/HMAC with a bu...
963
8.0
ARINC 429 IP Core
ARINC 429 IP Core implements ARINC 429 standard. IP Core contains Rx and Tx processing blocks, Controller Block, Internal Memory and External Memory I...
964
8.0
ARINC 429 IP Core
ARINC 429 IP Core implements ARINC 429 standard. IP Core contains Rx and Tx processing blocks, Controller Block, Internal Memory and External Memory I...
965
8.0
CRYSTALS Kyber core for accelerating NIST FIPS 203 Key Encapsulation Mechanism
eSi-Kyber is a hardware accelerator core designed to accelerate post-quantum Key Encapsulation Mechanism (KEM) as defined by NIST FIPS 203. Kyber, a...
966
7.0
Falcon IP Core
Falcon IP Core is a post-quantum digital signature algorithm (DSA). It is currently under development. It is going to be compliant with Falcon specifi...
967
7.0
ECDSA IP Core
ECDSA IP Cores perform digital signature generation and verification in compliance with the Elliptic Curve Digital Signature Algorithm (ECDSA) specifi...
968
7.0
AES GCM IP Core
AES GCM IP Core is a Secure Symmetric Block Cipher IP Core that has compliance with the Advanced Encryption Standard (AES) specification in "FIPS 197"...
969
7.0
AES IP Core
AES IP Core is a Secure Symmetric Block Cipher IP Core that has compliance with the Advanced Encryption Standard (AES) specification in "FIPS 197". Th...
970
7.0
SHA3 IP Core
SHA3 IP Cores perform cryptographic hashing in compliance with the SHA-3 (Secure Hash Algorithm 3) specifications defined in 'FIPS 202'. This standard...
971
7.0
Dilithium IP Core
Dilithium IP Core is a post-quantum digital signature algorithm (DSA). It currently supports Sign and Verify functions, with key generation functional...
972
7.0
DRBG IP Core
DRBG IP Cores perform deterministic random bit generation in compliance with the standards and guidelines defined in 'NIST SP 800-90A'. This standard ...
973
7.0
TRNG IP Core
TRNG IP Cores perform true random number generation in compliance with the standards and guidelines defined in 'NIST SP 800-90B'. This standard specif...
974
7.0
RSA IP Core
RSA IP Cores perform digital signature generation and verification in compliance with the RSA (Rivest-Shamir-Adleman) Digital Signature Algorithm spec...
975
7.0
RSA Keygen IP Core
RSA Keygen IP Cores perform key generation in compliance with the RSA Key Pair Generation specifications defined in 'FIPS 186'. This standard specifie...
976
7.0
USB 2.0 Full/Low-Speed Device Core
The FHG USB DEV is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate full-speed USB 2.0 device functionality wi...
977
7.0
USB 2.0 High/Full-Speed Device Core
The FHG USB2 DEV is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate high-/full-speed USB 2.0 device functiona...
978
7.0
USB 2.0 OTG Full/Low-Speed Dual Role Core
The FHG USB OTGDRD is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate full-/low-speed USB 2.0 device and host ...
979
7.0
USB 2.0 OTG High/Full/Low-Speed Dual Role Core
The FHG USB2 OTGDRD is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate high/full/low-speed USB 2.0 device and ...
980
7.0
KYBER IP Core
Kyber IP is a core designed for Kyber post-quantum Key Encapsulation Mechanism (KEM). It currently supports the Encapsulation and Decapsulation functi...
981
6.0
I2C Master/Slave Controller Core IP
I2C Master/Slave Controller core implements a bidirectional serial interface compatible with the NXP’s I2C bus specification and supports all transfer...
982
6.0
UART : Universal Asynchronous Receiver Transmitter Core
Universal Asynchronous Receiver Transmitter Core performs serial-to-parallel conversion on data characters received from a peripheral device or a MODE...
983
5.0
64-bit CPU Core with Level-2 Cache Controller
The 64-bit AX27L2 is a 5-stage processor that supports the latest RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit comp...
984
5.0
256-bit SHA Crypto Processor Core
The SHA-256 encryption IP core is a fully compliant implementation of the Message Digest Algorithm SHA-256. It computes a 256-bit message digest for m...
985
5.0
SATA Device IP Core (1.5, 3.0, 6.0 Gbps)
The Serial ATA Device Controller IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage ...
986
5.0
WAVE677DV PX4, AV1, H.265, HEVC, H.264, AVC, VP9 dual core video codec IP for 8K with YUV422, 444 support
WAVE677DV PX4 is a 4K/8K multi-standard video codec HW IP that supports AV1, HEVC/H.265, AVC/H.264, and VP9 standards. It provides 4K120fps@500MHz, 8K...
987
5.0
CCSDS AR4JA LDPC Decoder & Encoder IP Core
AR4JA LDPC decoder is a configurable design that allows runtime configuration for decoding different code rates (i.e., 1/2, 2/3 and 3/4). To obtain hi...
988
5.0
IEEE802.11n/ac/ax Wi-Fi LDPC Decoder and Encoder IP Core - silicon proven
The 802.11n/ac/ax LDPC decoder is developed for high throughput WLAN applications....
989
5.0
SerDes Hard Macro-IP in GlobalFoundries 22FDX
Low-power, flexible and robust Serializer-de-serializer IP built upon a proven ring-PLL based architecture, Support for multiple protocols, as well a...
990
5.0
AHB Cache Controller Core
The CACHE-CTRL IP core is a flexible cache memory controller providing a 32-bit slave AHB processor interface and a 32-bit master AHB interface to the...
991
5.0
The FortifyIQ Compact AES-SX AES Encryption Core with Robust SCA/FI Protection for Constrained Devices
FortifyIQ’s Compact AES IP Core is an ultra-lightweight hardware accelerator optimized for resource-constrained embedded systems that require secure e...
992
5.0
DiFi IP core
The DiFi IP core is a highly scalable and silicon agnostic implementation of the IEEE-ISTO Std 4900-2021: Digital IF Interoperability Standard v1.2.1 ...
993
5.0
High Throughput Elliptic Curve Cryptography hardware acceleration Core
eSi-ECDSA-HT is a High Throughput (HT) Elliptic Curve Cryptography (ECC) hardware acceleration core, which supports EC Digital Signature Algorithm (EC...
994
5.0
Time Sensitive Networking (TSN) IIC(R) Plugfest Application core
The TSN Industrial Internet Consortium(R) (IIC) Plugfest Application is a companion core for the TSN IP cores from NetTimeLogic. The IIC(R) Plugfest A...
995
5.0
MIPI RFFE Master IP Core
The MIPI RFFE Master controller IP is a highly optimized and technology agnostic implementation of the MIPI RFFE v.3.1 standard targeting both ASIC an...
996
5.0
MIPI RFFE Slave IP Core
The MIPI RFFE Slave controller IP is a highly optimized and technology and PHY agnostic implementation of the MIPI RFFE v.3.1 standard targeting both ...
997
5.0
Visually LossLess compression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS)
TMC’s JPEG XS encoder / decoder IP is Visually LossLess compression / decompression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS). T...
998
5.0
Visually LossLess decompression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS)
TMC’s JPEG XS encoder / decoder IP is Visually LossLess decompression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS). The logic gate ...
999
5.0
Ultra Compact 32-bit RISC-V CPU Core
AndesCore™ N22 is a 32-bit 2-stage pipeline CPU IP core based on AndeStar™ V5 architecture for embedded applications that require low energy consumpti...
1000
5.0
Compact High-Speed 32-bit CPU Core
AndesCore™ N25F is a 32-bit CPU IP core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it is capable of delivering high per-...