Design & Reuse
5606 IP
51
10.0
Voltage Monitor with Digital Output, TSMC N6
The voltage monitor is a low power self-contained IP block specially designed to monitor voltage levels within the core logic voltage domains and prov...
52
10.0
USB 1.1 Digital Controller IP
The Synopsys USB 1.1 Controllers support Full and Low Speed based on USB specification from the USB Implementer Forum. The Synopsys USB 1.1 IP offerin...
53
10.0
USB 2.0 Digital Controller IP
The Synopsys USB 2.0 Controllers support Hi-Speed (480 Mbps), Full Speed (12 Mbps), and Low Speed (1.5 Mbps) operation based on USB specification from...
54
10.0
USB 3.0 Digital Controller IP
The Synopsys SuperSpeed USB IP solution is implemented in hundreds of designs and shipped in millions of units. The USB IP solution is based on the US...
55
7.0
Display Controller - LCD / OLED Panels (AHB Bus)
The Digital Blocks DB9000AHB TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 2.0 AHB Bus to a TFT LCD pane...
56
7.0
Display Controller - LCD / OLED Panels (AHB-Lite Bus)
The Digital Blocks DB9000AHB-Lite TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 3.0 AHB-Lite Bus V1.0 to...
57
6.0
Display Controller - LCD 4K Digital Cinema (DCI)
The Digital Blocks DB9000AXI-DCI LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Interconne...
58
5.0
Temperature Sensor with Digital Output (High accuracy thermal sensing for reliability and optimisation), TSMC 28HPC+
A high precision low power junction temperature sensor that has been developed to be easily embedded into digital ASIC designs. The block features an ...
59
5.0
Temperature Sensor with Digital Output (High accuracy thermal sensing for reliability and optimisation), UMC 14FFC
A high precision low power junction temperature sensor that has been developed to be easily embedded into digital ASIC designs. The block features an ...
60
5.0
Voltage Monitor with Digital Output with Shrink, TSMC 28HPC+
The voltage monitor is a low power self-contained IP block specially designed to monitor voltage levels within the core logic voltage domains and prov...
61
5.0
SPI Master / Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS...
62
5.0
SPI Slave Controller (SPI2APB, SPI2AXI, SPI2AHB Bus)
The Digital Blocks DB-SPI-S-AMBA-BRIDGE is a Serial Port Interface (SPI) Controller Verilog IP Core supporting SPI Slave Interface to APB Master Bus. ...
63
5.0
eSPI & SPI Master/Slave Controller w/FIFO (APB, AHB, or AXI Bus)
The Digital Blocks DB-eSPI-SPI-MS-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI (eSPI...
64
5.0
AXI4 Multi-Channel DMA Controller (fixed 2,4,8,16 DMA Channels)
The Digital Blocks DB-DMAC-MC-AXI Verilog RTL IP Core is a Multi-Channel DMA Controller supporting 2, 4, 8, or 16 independent data transfers. The Dire...
65
3.0
I2C Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)
The Digital Blocks DB-I2C-MS-AHB Controller IP Core interfaces a microprocessor via the AHB system Interconnect Fabric to an I2C Bus. The I2C is a t...
66
3.0
I2C Master / Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-I2C-MS-APB Controller IP Core interfaces a microprocessor via the APB system Interconnect Fabric to an I2C Bus. The I2C is a t...
67
3.0
I2C Master Controller w/FIFO (APB Bus)
The Digital Blocks DB-I2C-M-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 AP...
68
3.0
I2C Slave Controller - Low Power, Low Noise Config of User Registers
The DB-I2C-S-SCL-CLK is an I2C Slave Controller IP Core focused on low power, low noise ASIC / ASSP designs requiring the configuration & control of r...
69
3.0
I2C Slave Controller w/FIFO (APB or AHB or AHB-Lite or AXI-Lite Bus)
The Digital Blocks DB-I2C-S-APB / DB-I2C-S-AHB / DB-I2C-S-AXI / DB-I2C-S-AVLN Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC,NIOS II or othe...
70
3.0
I2C Slave with AHB Master Bridge (I2C2AHB)
The DB-I2C-S-AHB-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & c...
71
3.0
I2C Slave with APB Master Bridge (I2C2APB)
The DB-I2C-S-APB-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & c...
72
3.0
I2C Slave with AXI Master Bridge (I2C2AXI4)
The DB-I2C-S-AXI-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & c...
73
3.0
2D Graphics Hardware Accelerator (AXI4 Bus)
The DB9200AXI4 2D Graphics Engine Verilog IP Core targets low VLSI footprint, high-performance hardware accelerated graphics applications. The DB92...
74
3.0
Hs-Mode I2C Controller - 3.4 Mbps, Master / Slave w/FIFO
The Digital Blocks DB-I2C-MS-Hs-Mode Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus or Avalon / Qsys Bus to an I2C Bu...
75
2.0
I3C Master / Slave Controller - MIPI Basic v1.0
The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – BASIC ...
76
2.0
MIPI D-PHY Digital Front-End for FPGA
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
77
1.0
I2C Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)
The Digital Blocks DB-I2C-MS-AXI Controller IP Core interfaces a microprocessor via the AXI system Interconnect Fabric to an I2C Bus. The I2C is a t...
78
1.0
BitBLT Graphics Hardware Accelerator (AHB Bus)
The Digital Blocks DB9100AHB BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to ...
79
1.0
BitBLT Graphics Hardware Accelerator (AXI Bus)
The Digital Blocks DB9100AXI3 BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to...
80
1.0
RTP / UDP / IP Hardware Stack for H.264/H.265 NAL Video Streams Packet Processing
The Digital Blocks DB-RTP-UDP-IP-NAL IP Core is a RTP/UDP/IP Protocol Hardware Stack with MAC Layer Pre- & Post-Processors and an ARP Packet Processor...
81
1.0
RTP / UDP / IP Hardware Stack for Raw, Uncompressed RGB/YUV Video Streams
The Digital Blocks DB-RTP-UDP-IP-AV IP Core is a RTP/UDP/IP Protocol Hardware Stack with MAC Layer Pre- & Post-Processors and an ARP Packet Processor ...
82
0.3729
1.8V Secondary Oxide Programmable DLL, fully digital DLL - TSMC 22nm 22ULP,ULL
Dolphin Technology offers a wide range, programmable PLL Compiler designed to provide low jitter across PVT variations. Dolphin also provides a fully ...
83
0.3729
1.8V Secondary Oxide Programmable DLL, fully digital DLL - TSMC 28nm 28HP, 28LP, 28ULP, 28HPL, 28HPC, 28HPC+, 28HPM
Dolphin Technology offers a wide range, programmable PLL Compiler designed to provide low jitter across PVT variations. Dolphin also provides a fully ...
84
0.3729
Digital Delay Locked Loop (133MHz - 333MHz) - TSMC 90nm GT (CLN90GT)
Dolphin Technology offers a wide range, programmable PLL Compiler designed to provide low jitter across PVT variations. Dolphin also provides a fully ...
85
0.3729
Digital Delay Locked Loop (133MHz – 333MHz) - TSMC 80nm GC (CLN80GC)
Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully complian...
86
0.3729
Digital Delay Locked Loop (133MHz – 333MHz) - TSMC 90nm G (CLN90G)
Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully complian...
87
0.3729
Digital Delay Locked Loop (133MHz – 333MHz) - TSMC 90nm GT (CLN90GT)
Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully complian...
88
0.3729
Digital Delay Locked Loop (133MHz – 333MHz) - TSMC 90nm LP (CLN90LP)
Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully complian...
89
0.3729
Digital Delay Locked Loop (133MHz – 333MHz) - TSMC 80nm 80GC,LP_EMF
Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully complian...
90
0.3729
Digital Delay Locked Loop (133MHz – 333MHz) - TSMC 90nm 90G,GT,LP
Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully complian...
91
0.3729
Programmable DLL, fully digital DLL - TSMC 12nm 12FFC,FFC+
Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, S...
92
0.3729
Programmable DLL, fully digital DLL - TSMC 16nm 16FFC,FF
Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, S...
93
0.3729
Programmable DLL, fully digital DLL - TSMC 3nm
Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, S...
94
0.3729
Programmable DLL, fully digital DLL - TSMC 40nm 40G,LP,LP_eF,ULP,ULP_eF - UMC 40ULP
Dolphin Technology offers a wide range, programmable PLL Compiler designed to provide low jitter across PVT variations. Dolphin also provides a fully ...
95
0.3729
Programmable DLL, fully digital DLL - TSMC 4nm 4FF/4P
Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, S...
96
0.3729
Programmable DLL, fully digital DLL - TSMC 55nm 55GP,LP,LP_EMF,ULP,ULP_EMF
Dolphin Technology offers a wide range, programmable PLL Compiler designed to provide low jitter across PVT variations. Dolphin also provides a fully ...
97
0.3729
Programmable DLL, fully digital DLL - TSMC 5nm 5FF
Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, S...
98
0.3729
Programmable DLL, fully digital DLL - TSMC 65nm 65GP,LP,LP_EMF
Dolphin Technology offers a wide range, programmable PLL Compiler designed to provide low jitter across PVT variations. Dolphin also provides a fully ...
99
0.3729
Programmable DLL, fully digital DLL - TSMC 6nm 6FF
Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, S...
100
0.3729
Programmable DLL, fully digital DLL - TSMC 7nm 7FF,FF+
Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, S...