Design & Reuse
5606 IP
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0.3729
Programmable DLL, fully digital PLL - TSMC 28nm 28HP (CLN28HP)
Dolphin Technology offers a wide range, programmable PLL Compiler designed to provide low jitter across PVT variations. Dolphin also provides a fully ...
102
0.3729
Programmable DLL, fully digital PLL - TSMC 40nm 40G (CLN40G)
Dolphin Technology offers a wide range, programmable PLL Compiler designed to provide low jitter across PVT variations. Dolphin also provides a fully ...
103
0.3729
Programmable DLL, fully digital PLL - TSMC 40nm 40LP (CLN40lp)
Dolphin Technology offers a wide range, programmable PLL Compiler designed to provide low jitter across PVT variations. Dolphin also provides a fully ...
104
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4-bit, 10 GSPS Analog to Digital Converter (ADC) IP block STMicroelectronics 28nm
The A4B10G is a low-power, high-speed analog to digital converter (ADC) intellectual property (IP) design block. It is a flash-type ADC, with 4-bit re...
105
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4-bit, 20 GSPS Analog to Digital Converter (ADC) IP block STMicroelectronics 28nm
The A4B20G is a low-power, high-speed analog to digital converter (ADC) intellectual property (IP) design block. It is a flash-type ADC, with 4-bit re...
106
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8-bit, 40 GSPS Analog to Digital Converter (ADC) IP block STMicroelectronics 28nm
The A8B40G is a low-power, high-speed analog to digital converter (ADC) intellectual property (IP) design block. It is a time-interleaved successive ...
107
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A12B25M-XS180, Analog to Digital Converter (ADC) IP Block XFab 180nm
The A12B25M is an ultra low-power, high-performance analog to digital converter (ADC) intellectual property (IP) design block. It is a pipeline ADC th...
108
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12-bit, 1.5 MSPS Analog-to- Digital Converter (ADC) X-FAB 180nm
The A12B1p5M is a low-power analog to digital converter (ADC) intellectual property (IP) design block. It is a successive approximation register (S...
109
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I2C Master Controller w/FIFO (AHB & AHB-Lite Bus)
The Digital Blocks DB-I2C-M-AHB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 AP...
110
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I2C Master Controller w/FIFO (AXI & AXI-Lite Bus)
The Digital Blocks DB-I2C-M-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 AX...
111
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I2C Slave Controller - Low Power, Low Noise Config with APB Interface
The Digital Blocks DB-I2C-S-SCL-CLK-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA...
112
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I2C Slave Controller w/FIFO (AHB Bus)
The Digital Blocks DB-I2C-S-AHB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2.0/3.0...
113
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I2C Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-I2C-S-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2.0 APB...
114
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I2C Slave Controller w/FIFO (AXI Bus)
The Digital Blocks DB-I2C-S-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 4/3 AXI...
115
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I2C Slave Controller with User Register Array / Memory / FIFO / AMBA Interface
The DB-I2C-S-REG is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs interfacing to user registers while autonomous i...
116
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I2C/SMBus Master/Slave Controller w/FIFO (AXI/AHB/APB)
The Digital Blocks DB-I2C-SMBus-MS-AMBA Controller IP Core is an I2C/SMBus Master/Slave Controller, interfacing a microprocessor via the AMBA AXI, AHB...
117
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I3C Master / Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improv...
118
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I3C Master Controller w/FIFO (APB Bus)
The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improv...
119
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I3C Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-I3C-S-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improve...
120
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14-bit 80MSPS Flash Analog to Digital Converter (ADC) IP Block UMC 90nm
The A14B80M is an ultra low-power, high-performance analog to digital converter (ADC) intellectual property (IP) design block. It has 14-bit resoluti...
121
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Walnut DSA (TM) Fast, Future-Proof Digital Signature Algorithm Designed for Low-Resource Devices
WalnutDSA™ is a fast, small footprint, future-proof, public-key digital signature solution for low-resource devices–running on 8-, 16-, an...
122
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Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers
The Digital Blocks DB-DMAC-MC-AXI4-MM-STREAM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Mem...
123
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Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers
The Digital Blocks DB-DMAC-MC-AXI4-MM-STREAM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Mem...
124
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LCD Controller - TFT LCD Panels (AXI4 Bus)
The Digital Blocks DB9000AXI4 TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 4.0 AXI4 Protocol Interconne...
125
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CCIR 656 Decoder
The Digital Blocks DB1840 CCIR 656 Decoder IP Core decodes an ITU-R BT.656 digital video uncompressed NTSC 720x486 (525/60 Video System) and PAL 720x5...
126
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CCIR 656 Encoder
The Digital Blocks DB1830 CCIR 656 Encoder IP Core encodes 4:2:2 Y’CbCr component digital video with synchronization signals to conform to NTSC & PAL ...
127
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2D Graphics Rendering Engine
Digital Blocks 2D Graphics Hardware Accelerator Verilog IP Cores consists of the DB9200AXI4, DB9200AXI, DB9200AHB, and DB9200AVLN. The DB9200 2D Graph...
128
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UDP/IP Hardware Protocol Stack - 100G
The Digital Blocks DB-UDP-IP-100GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 100 GbE n...
129
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UDP/IP Hardware Protocol Stack - 10G
The Digital Blocks DB-UDP-IP-10GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 10 GbE net...
130
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UDP/IP Hardware Protocol Stack - 1G
The Digital Blocks DB-UDP-IP-1GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 10 GbE netw...
131
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UDP/IP Hardware Protocol Stack - 25G
The Digital Blocks DB-UDP-IP-25GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 25 GbE net...
132
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UDP/IP Hardware Protocol Stack - 40G
The Digital Blocks DB-UDP-IP-40GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 50 GbE net...
133
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UDP/IP Hardware Protocol Stack - 50G
The Digital Blocks DB-UDP-IP-50GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 50 GbE net...
134
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GF 6-bit, 12 GSPS Analog to Digital Converter (ADC) IP block GlobalFoundries 22nm
The A6B12G is a low-power, high-speed analog to digital converter (ADC) intellectual property (IP) design block. It is a FLASH-type ADC, with 6-bit re...
135
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RGB to CCIR 601 / 656 Encoder
The Digital Blocks DB1892AXI RGB to CCIR 601 / CCIR 656 Encoder interfaces RGB data along with synchronization signals from a LCD Controller such as D...
136
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RGB to CCIR601/656 Encoder
The Digital Blocks DB1892AXI RGB to CCIR 601 / CCIR 656 Encoder interfaces RGB data along with synchronization signals from a LCD Controller (or any L...
137
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Video Sync Separator IP
The Digital Blocks DB1800 Video Sync Separator IP Core extracts timing information from a standard NTSC/PAL/SECAM composite sync video signal. The DB1...
138
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Digital Blocks - SoC Design services
Digital Blocks architects, designs, verifies, and markets semiconductor IP cores to worldwide technology systems companies. We Can Customize Our IP ...
139
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Digital Cinema LCD Controller
The Digital Blocks DB9000AXI-DCI LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Interconne...
140
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BitBLT Graphics Hardware Accelerator (AXI4 Bus)
The Digital Blocks DB9100AXI4 BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to...
141
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BitBLT Graphics Hardware Accelerator Engine
The DB9100 BitBLT 2D Graphics Engine IP Core (Verilog Cores DB9100AXI4, DB9100AXI, DB9100AHB, DB9100AVLN) reads graphics command sets originated by th...
142
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All Digital Phase Locked Loop
The iniADPLL is an all digital implementation of a phase locked loop. Plls are widely used in telecom applications for clock recovery, clock generatio...
143
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DMA AXI4-Stream Interface to AXI Memory Map Address Space
Digital Blocks DB-AXI4-STREAM-TO-AXI4-MM-BRIDGE Verilog RTL IP Core accepts AXI4-Stream data and control input, converts the control TID to a AXI4 Mem...
144
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Color Space Converter & Chroma Resampler
The Digital Blocks DB1825 Color Space Converter & Chroma Resampler Verilog IP Core transforms 4:4:4 sampled RGB color components to 4:4:4 Y’CbCr color...
145
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Compact High Frequency Digital Frequency Divider
Kamaten high frequency divider reduces/divides input digital signal (clock) frequency and can be set to any integer division ratio from 1 to 512. Divi...
146
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Compact Low Power Digital Frequency Divider
Kamaten low power frequency divider reduces/divides input digital signal (clock) frequency and can be set to any integer division ratio from 1 to 64. ...
147
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FPD LVDS Display Interface - 1 & 2 Port LVDS Panels
The Digital Blocks DB-FPD-LVDS-TX LVDS Display Interface IP Core interfaces parallel 18-bit/24-bit RGB Pixel Data with display timing VSYNC, HSYNC, Da...
148
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SPI Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)
The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS...
149
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SPI Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)
The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS...
150
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SPI Master Controller w/FIFO (AHB & AHB-Lite Bus)
The Digital Blocks DB-SPI-M is a Serial Port Interface (SPI) Controller Verilog IP Core supporting only Master SPI Bus transfers (both Full Duplex and...