Design & Reuse
Catalog of SIP Cores
System on Chip design resources
3747 IP
1
130.0
LPDDR6, LPDDR5X Combo PHY & Controller
INNOSILICON™ introduces its LPDDR6/5X PHY and Controller IP, purpose-built for the AI era’s high-performance chip design needs. This solution is fully...
2
100.0
1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
eTopus designs ultra-high speed mixed-signal semiconductor IP solutions for high-performance computing and data center applications. Our 1-56/112Gbps ...
3
100.0
400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
...
4
100.0
56G Serdes in 7nm bundled with PCie Gen 5 controller IP
New IP for value conscious designers....
5
100.0
PCIe 5.0 PHY & Controller
The Innosilicon Gen1/2/3/4/5 PCI Express Controller provides a PCI Express Root Complex (RC) and Endpoint (EP) application. It’s a high performance, h...
6
100.0
PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
Multiprotocol low latency, low power SERDES IP....
7
100.0
Complete USB Type-C Power Delivery PHY, RTL, and Software
The OTI9108 is a complete single transceiver front end for data USB PD Type-C (baseband) communications. It has a register interface which, with an MP...
8
100.0
LPDDR5X, LPDDR5, LPDDR4X, LPDDR4 Combo PHY & Controller
The INNOSILICON™ LPDDR IP includes a LPDDR5X/5/4X/4 Combo PHY and controller. It is fully compliant with the JEDEC standard. Optimized for low-power a...
9
80.0
GDDR7 PHY & Controller
The INNOSILICON™ GDDR7 PHY is fully compliant with the JEDEC GDDR7 standard, supporting data rates of up to 32 Gbps in PAM3 mode. In PAM3 mode, each b...
10
80.0
LPDDR5X/5/4X combo PHY at Samsung 8LPU
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
11
80.0
LPDDR6/5X/5 combo PHY at Samsung SF4X
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
12
80.0
LPDDR6/5X/5/4X/4 Memory Controller IP
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
13
60.0
UCIe Chiplet PHY & Controller
INNOSILICON™ UCIe Chiplet IP offers a customizable solution for seamless, low-latency data transfer between silicon dies and chips, enabling heterogen...
14
60.0
IGAHBMV03A, TSMC CLN16FFC HBM PHY with CoWoS technology
IGAHBMV03A, TSMC CLN16FFC HBM PHY with CoWoS technology...
15
60.0
LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
16
50.0
512x8 Bits OTP (One-Time Programmable) IP, TSM- 12FFC 0.8V/1.8V Process
The ATO00512X8TS012FFC8EA is organized as 512 bits by 8 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in 12nmFFC stand...
17
50.0
DDR4/3, LPDDR5x/5/4x/4 Memory Controller IP
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
18
50.0
High Bandwidth Out-of-Order RISC-V CPU IP Core
...
19
50.0
High Bandwidth Out-of-Order RISC-V CPU IP Core
...
20
50.0
Nuclei NA900: ASIL-B/D compliant 32/64-bit safety-certified 9-stage-pipeline processor for automotive and safety-critical applications
As the world’s first RISC-V CPU IP fully compliant with ISO 26262 ASIL-B/D certification, it is a dual-issue, in order execution core engineered for ...
21
46.0
32Gbps, 31 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter
This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 31 order, up to 32Gbps. Error count is accurate: no double counts or omissions reg...
22
46.0
32Gbps, 7/15 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter
This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 7 or 15 order, up to 32Gbps. Error count is accurate: no double counts or omission...
23
46.0
32Gbps, 7/15/31 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter
This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 7, 15 or 31 order, up to 32Gbps. Error count is accurate: no double counts or omis...
24
30.0
UCIe Die-to-Die Chiplet Controller
Introducing OPENEDGES’ Universal Chiplet Interconnect Express (UCIe) Controller IP, OUC, designed to transform the semiconductor landscape with innova...
25
30.0
UFS Host Controller 4.1 IP
The UFS Host Controller Interface (UFSHCI) is a high-performance interface that connects to UniPro and M-PHY IP in mobile platforms. It provides comma...
26
30.0
High speed NoC (Network On-Chip) Interconnect IP
OPENEDGES is the only total memory system IP company providing both memory controller and on-chip interconnect. OIC is the ORBIT high-speed On-chip In...
27
30.0
RISC-V Tensor Unit
The bulk of computations in Large Language Models (LLMs) is in fully-connected layers that can be efficiently implemented as matrix multiplication. Th...
28
30.0
All in one solution for AI in RISC-V
...
29
30.0
Nuclei N900(SMP): 32-bit high-efficiency 9-stage-pipeline processor with DSP/FPU capable for embedded and real-time applications
32-bit high-performance RISC-V core, belonging to Nuclei 900 Series, optimized for high-performance embedded scenarios without MMU. Comparable to ARM ...
30
30.0
Nuclei NA300: ASIL-B/D compliant 32-bit safety-certified 3-stage-pipeline processor for automotive and safety-critical applications
Low-Power Automotive-Grade RISC-V Processor Core Compliant with ISO 26262 ASIL D/B standards, it features a highly configurable architecture designed...
31
30.0
Nuclei UX1000 Series: High-performance Out-of-Order processor for Linux-capable applications with virtualization supported
A commercial RISC-V processor core series by Nuclei for real-time and high-performance applications, competing with ARM Cortex-R82/A72/A73/A76/A78. O...
32
29.0
USB V3.1 Power Delivery Type-C Port Evaluation board for OTI9108 IP
The OTS9106 board is a complete FPGA and ARM processor based USB PD Type-C port, featuring the RTL and C source code of the Obsidian Technology OTI910...
33
25.0
HBM4, HBM3E PHY & Controller
INNOSILICON™ HBM4/3E IP is fully compliant with the JEDEC standard for HBM3E and the preliminary specification for HBM4. The IP includes a customizabl...
34
25.0
DDR5, DDR4 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal DDR5/4 Combo PHY s provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDR...
35
25.0
Superscalar Out-of-Order Execution Multicore Cluster
AndesCore™ AX65 64-bit multicore CPU IP is a high-performance quad decode 13-stage superscalar out-of-order processor based on AndeStar™ V5 architectu...
36
20.0
100Base-T1 Automotive Ethernet PHY
100Base-T1 Automotive Ethernet PHY...
37
20.0
D2D(UCIe 1.0)
The Die-to-Die interface is a functional block that provides a data interface between two chip dies in the same package. MSquare's M2LINK D2D Solution...
38
20.0
D2D(UCIe 1.1)
The Die-to-Die interface is a functional block that provides a data interface between two chip dies within the same package. MSquare's D2D solution, c...
39
20.0
HBM3 IP
MSquare's HBM3 IP (the 3rd generation of High-Bandwidth Memory) is specifically tailored for applications that require high memory throughput and low ...
40
20.0
PCIe 4.0 PHY
MSquare's PCI Express 4.0 PHY IP includes a high-speed, highly-efficient, and cost-effective transceiver to turbocharge today's high-performance and h...
41
20.0
PCIe 4.0 PHY in TSMC(6nm,7nm,12nm,16nm)
M31 PCIe 4.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. The PCIe 4.0 IP suppo...
42
20.0
PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection
M31 PCIe 5.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. The PCIe 5.0 IP suppo...
43
20.0
eDP PHY
MSquare's eDP PHY is a highly reliable solution for display interface requirements, supporting resolutions of 4K and higher. By operating at substanti...
44
20.0
High Performance HBM, HBM3 Memory Controller
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
45
20.0
MIPI C-PHY/D-PHY Combo(5nm, 7nm, 12/16nm, 28nm, 40nm, 55nm)
MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices. To further improve thr...
46
20.0
MIPI M-PHY v4.1/v3.1 IP in TSMC(5nm, 6nm, 7nm, 12nm,16nm, 22nm, 28nm, 40nm, and 55nm)
MIPI M-PHY is a serial interface technology with high bandwidth capabilities, which is particularly developed for mobile applications to obtain low pi...
47
20.0
ONFI 5.0 PHY IP
MSquare offers a silicon-proven ONFI 5.0 PHY IP which supports all modes of the Open NAND Flash Interface (ONFI) 5.0 Specification. ONFI is an interfa...
48
20.0
ONFI 5.1 PHY IP
MSquare's ONFI 5.1 PHY is a high-performance and low-power PHY IP, which supports all modes of the Open NAND Flash Interface (ONFI) 5.1 specification....
49
20.0
LPDDR4/3, DDR4/3 Memory Controller IP
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
50
20.0
LPDDR4X PHY
MSquare's LPDDR4X PHY is a transceiver physical layer IP interface solution designed for ASICs and SOCs. Compatible with the universal IP protocol DFI...