Design & Reuse
3706 IP
3651
0.0
Low Power Stereo Audio CODEC
Innosilicon Codec is a low power, high resolution, stereo CODEC solution which employs Sigma-Delta noise-shaping technique. The ADC, DAC and power amp...
3652
0.0
Low Power Stereo Audio CODEC_2ADC1DAC
Innosilicon Codec is a low power, high resolution, stereo CODEC solution which employs Sigma-Delta noise-shaping technique. The ADC, DAC and power amp...
3653
0.0
Low Power Stereo Audio CODEC_2ADC2DAC
Innosilicon Codec is a low power, high resolution, stereo CODEC solution which employs Sigma-Delta noise-shaping technique. The ADC, DAC and power amp...
3654
0.0
Low Power Stereo Audio CODEC_4ADC4DAC
Innosilicon Codec is a low power, high resolution, stereo CODEC solution which employs Sigma-Delta noise-shaping technique. The ADC, DAC and power amp...
3655
0.0
Low Power Stereo Audio CODEC_80db
Innosilicon Codec is a low power, stereo CODEC solution which employs Sigma-Delta noise-shaping technique. The ADC, DAC and power amplifier are integr...
3656
0.0
Low Power Stereo Audio CODEC_90dB
Innosilicon Codec is a low power, high resolution, stereo CODEC solution which employs Sigma-Delta noise-shaping technique. The ADC, DAC and power amp...
3657
0.0
Power on Reset IP, Input: 1.2V, UMC 0.13um HS/FSG process
Vrr=0.8V Vfr=0.65V, VCC=1.2V, Ivcc=12.7uA, HS process with B-type IO., Power On Reset, UMC 0.13um HS/FSG Logic process....
3658
0.0
Power-On-Reset IP
INNOSILICON™ Power-On-Reset (POR) IP provides reliable reset functions for a variety of applications. It is powered by an analog supply and monitors b...
3659
0.0
DP/eDP PHY + Controller
INNOSILICON™ DP/eDP IP is designed for transmitting or receiving video and audio signals between the video source devices and display devices. It is f...
3660
0.0
DP1.1 RX PHY
Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. ...
3661
0.0
DP1.2 RX PHY
Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. ...
3662
0.0
DP1.2 Transmitter PHY
Innosilicon DP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications. In...
3663
0.0
DP1.2 Transmitter PHY_40nm
Innosilicon DP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications. In...
3664
0.0
DP1.4 Receiver Controller
This document describes the low power Innosilicon DP 1.4 Receiver controller, which is fully compliant with DP 1.4 specification and eDP 1.4 standard....
3665
0.0
DP1.4 TX PHY
Innosilicon eDP TX PHY is designed to transmit video, audio, and auxiliary data from a system host device to a display device for display applications...
3666
0.0
LPDDR2 PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR2 PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devi...
3667
0.0
LPDDR3/2 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR3/2 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SD...
3668
0.0
LPDDR3/2/DDR3/3L Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR2/3/DDR3/3L COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compa...
3669
0.0
LPDDR3/2/DDR3/3L/2 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR3/2/DDR3/3L/2 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC com...
3670
0.0
LPDDR4/DDR4/DDR3 PHY - TSMC 22nmULL
SP-LPD4/D43_PHY16BIT-T22ULL is designed for DRAM controller to connect to the LPDDR4/DDR4/3 DRAM memory device. It contains a DDR PHY Control Unit(DPC...
3671
0.0
LPDDR4X, LPDDR4, DDR4, LPDDR3 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR4/4X/DDR4/LPDDR3 PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compat...
3672
0.0
LPDDR4X/4/3/DDR4/3/3L PHY + Controller
INNOSILICON™ LPDDR4X/4/3/DDR4/3/3L Combo IP is a customizable Mixed-Signal DDR memory interface suite. The Combo IP provides turnkey physical interfac...
3673
0.0
LPDDR5/4x/4 PHY IP for Samsung 14LPU
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
3674
0.0
LPDDR6, LPDDR5X Combo PHY & Controller
INNOSILICON™ introduces its LPDDR6/5X PHY and Controller IP, purpose-built for the AI era’s high-performance chip design needs. This solution is fully...
3675
0.0
Specialty SSTL IO IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process true 2.5V SSTL2 IO cells....
3676
0.0
CPU IP - Follows the RVA23 Profile, supports RVV1.0 and supports all extensions of Vector Crypto
StarFive Dubhe-83 CPU IP features a 10+ stage pipeline, 3-issue, and out-of-order pipeline, follows the RVA23 Profile, supports RV64GCBVH, supports RV...
3677
0.0
MRDIMM DDR5 & DDR5/4 PHY & Controller
INNOSILICON™ DDR5 IP includes the MRDIMM DDR5 PHY and DDR5/4 Combo PHY and corresponding controllers for ICs requiring access to JEDEC compatible SDRA...
3678
0.0
Process/Voltage/ Temperature Sensor
INNOSILICON™ PVT Sensor IP is designed for on-chip monitoring of processes, voltage, and temperature variations. It is a critical component in modern ...
3679
0.0
ARP/ICMP Protocol for Ethernet
The CT1006-XGARP/ICMP block adds RTL-hardened functions for ICMP and ARP to any FPGA application. The all-RTL block includes part of the ARP protoc...
3680
0.0
ARTIEYE Driver Monitoring System (DMS) Technology Suite
Driver Monitoring Systems (DMS) reduce the number of car accidents related to driver drowsiness and distraction, and make roads safer for everyone. DM...
3681
0.0
USB 2.0/1.1 PHY (6nm, 7nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm, 65nm, 90nm)
USB 2.0 PHY M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power consumptio...
3682
0.0
USB BCK Technology (22nm, 40nm, 55nm, 110nm)
In USB product series, M31 not only provides customers with a standard USB PHY solution, but also offers a unique BCK function. M31’s patented BCK (Bu...
3683
0.0
USB Type-C and Power deliver Controller
USB Type-C and Power deliver Controller...
3684
0.0
HSIC PHY
The Innosilicon HSIC PHY is fully compliant with the High-Speed Inter-Chip Supplement to the USB 2.0 Specification. By stripping off all the legacy US...
3685
0.0
PSRAM PHY
The INNOSILICON DDR IPTM Mixed-Signal PSRAM PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible PSRAM devic...
3686
0.0
PSRAM/RPC PHY & Controller
INNOSILICON™ PSRAM IP consists of a configurable PHY and RPC PHY and a controller. It provides the physical interface solutions for ICs requiring acce...
3687
0.0
JTAG 2-Wire to 4-Wire Adapter
The OT4001_cjtag is an adapter which permits legacy IEEE 1149.1 ports to communicate as an IEEE 1149.7 2-wire OScan1 cJTAG port. A simple update to a ...
3688
0.0
LTE UE PHY layer
The PHY baseband covers all Synchronization Signals, downlink and uplink Physical Channels, libraries, algorithms integrated with cross-functional log...
3689
0.0
LTE UE Protocol Stack HW (Arm, Cortex A8)
Mymo offers 3GPP LTE Release-9 UE FDD and TDD UE Protocol Stack on Arm hardware . The Integrated solution of MAC-RLC-PDCP-RRC-NAS-TCP-IP with several ...
3690
0.0
LTE UE Protocol Stack Software
Mymo offers 3GPP LTE Release-9 UE FDD and TDD UE Protocol Stack software. The software is in ANSI C ported at RT-Linux kernel level ideally suited for...
3691
0.0
Successive Approximation ADC_2M10b
Innosilicon SARADC IP is a small-sized, low power analog to digital converter with input channels. The converter is a charge-redistribution successive...
3692
0.0
Successive Approximation ADC_2M12b
Innosilicon SAR-ADC IP is a small-size, low power analog to digital converter. The converter is a charge-redistribution successive approximation ADC. ...
3693
0.0
Successive Approximation ADC_3M10b
Innosilicon SARADC IP is a small-sized, low power analog to digital converter with input channel and Standard I/O multiplexed. The converter is a char...
3694
0.0
Audio Codec
INNOSILICON™ Audio Codec IP is a low power, high resolution, stereo audio solution which leverages Sigma-Delta noise-shaping technology. The ADC, DAC,...
3695
0.0
PUF Security
A physical unclonable function, or PUF, is a "digital fingerprint" that serves as a unique identity for a semiconductor device such as a microprocesso...
3696
0.0
eUSB2 PHY
The industry’s most advanced process nodes do not support 3.3V signaling and 5V tolerance as required by the USB 2.0 specification. 3.3V signaling was...
3697
0.0
JVC_4K Adoptive Scaler + Super Resolution - Convert Full-HD to High quality 4k2k with super resolution technology
JVC s 4k2k Super Resolution IP is now available for licensing. It offers dramatically less jaggy and Full-HD to 4k2k up-conversion with high performan...
3698
0.0
LVDS RX PHY & Controller
Innosilicon LVDS implements LVDS TIA/EIA protocol. It specifies a low-voltage point-to-point signal interface, which uses a differential driver connec...
3699
0.0
LVDS TX Combo TTL PHY
Innosilicon LVDS implements LVDS TIA/EIA protocol. Normally, Innosilicon LVDS contains four 7-bit parallel-load serial-out shift registers, a 7X clock...
3700
0.0
LVDS TX PHY & Controller
Innosilicon LVDS implements LVDS TIA/EIA protocol. It specifies a low-voltage point-to-point signal interface, which uses a differential driver connec...