Design & Reuse
3706 IP
3701
0.0
LVDS/TTL PHY & Controller
INNOSILICON™ LVDS/TTL IP implements the LVDS TIA/EIA protocol, providing a low-voltage, high-speed point-to-point signal interface. It supports either...
3702
0.0
Two Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP/ Low-K process, Two Port Register File memory compiler....
3703
0.0
1x32 Bits OTP (One-Time Programmable) IP, TSM- 0.18μm SiGe BiCMOS 1.8V/3.3V Process
The ATO0001X32TS180SGE3NA is organized as 1 by 32 bits one-time programmable (OTP). This is a kind of non-volatile memory fabricated in 0.18um SiGe Bi...
3704
0.0
1x64 Bits OTP (One-Time Programmable) IP, TSM- 0.18μm Mixed-Signal 1.8V/3.3V Process
The AT1X64T180MM0AB is organized as one by 64 bits one-time programmable (OTP). This is a kind of non-volatile memory fabricated in TSM- Mixed-Signal ...
3705
0.0
Cyber Protection Technology for MIL-STD-1553, CAN Bus and ARINC825
Aircraft and car makers rely on inbound communication networks to reliably exchange real-time information between the dozens of ECUs and Avionic syste...
3706
0.0
Type-C PHY
Innosilicon Type-C IP is composed of the physical layer and the PHY logic. The physical layer contains 4 data channels, an AUX channel and bias circui...