Eureka Technology, Inc. IP Cores

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100.0

The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.

SuperFlash® is SST’s patented and proprietary NOR flash technology. With 80B+ devices shipped, SuperFlash is the non-volatile memory of choice for emb...

70.0

DDR4/3, LPDDR5x/5/4x/4 Memory Controller IP

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

70.0

LPDDR5X/5/4X/4 combo PHY at Samsung SF5A

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

70.0

LPDDR5X/5/4X/4 Memory Controller IP

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

50.0

LPDDR5/4x/4 combo PHY on 14nm, 12nm

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

46.0

32Gbps, 31 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter

This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 31 order, up to 32Gbps. Error count is accurate: no double counts or omissions reg...

46.0

32Gbps, 7/15 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter

This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 7 or 15 order, up to 32Gbps. Error count is accurate: no double counts or omission...

46.0

32Gbps, 7/15/31 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter

This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 7, 15 or 31 order, up to 32Gbps. Error count is accurate: no double counts or omis...

40.0

LPDDR5X/5/4X/4 combo PHY at 7nm

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

40.0

LPDDR5X/5/4X/4 PHY for 16nm

The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...

40.0

LPDDR5X/5/4X/4 PHY IP for 12nm

The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...

30.0

4-/8-bit mixed-precision NPU IP

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

30.0

UCIe Die-to-Die Chiplet Controller

Introducing OPENEDGES’ Universal Chiplet Interconnect Express (UCIe) Controller IP, OUC, designed to transform the semiconductor landscape with innova...

30.0

High speed NoC (Network On-Chip) Interconnect IP

OPENEDGES is the only total memory system IP company providing both memory controller and on-chip interconnect. OIC is the ORBIT high-speed On-chip In...

30.0

Highly scalable inference NPU IP for next-gen AI applications

OPENEDGES, the total memory subsystem IP provider, introduces ENLIGHT Pro, a state-of-the-art inference neural processing unit (NPU) IP that outperfor...

20.0

GDDR6 Memory Controller IP

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

20.0

High Performance HBM, HBM3 Memory Controller

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

20.0

LPDDR4/3, DDR4/3 Memory Controller IP

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

20.0

LPDDR4x/4 PHY IP for 22nm

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

20.0

LPDDR5X/5/4X/4 combo PHY at 12nm

The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...

11.0

NVM Anti-Fuse OTP NeoFuse in DBHitek(90nm)