Design & Reuse
8402 IP
51
11.0
NVM eFlash NeoFlash in Vanguard (160nm)
eMemory's NeoFlash IP is a cost-effective embedded Flash solution for both foundries & customers. Only 2~3 additional masks are required, and NeoFlash...
52
11.0
NVM eFlash RRAM in UMC (40nm)
eMemory's RRAM IP is a cost-effective embedded Flash solution for both foundries & customers. Only 2~3 additional masks are required, and RRAM gives f...
53
11.0
NVM MTP NeoMTP in DBHitek(180nm, 130nm)
NeoMTP is a single-poly embedded memory technology offering high NVM memory density with 1K endurance at the lowest implementation cost to be found in...
54
11.0
NVM MTP NeoMTP in GLOBALFOUNDRIES (130nm)
NeoMTP is a single-poly embedded memory technology offering high NVM memory density with 1K endurance at the lowest implementation cost to be found in...
55
11.0
NVM MTP NeoMTP in Grace (180nm)
NeoMTP is a single-poly embedded memory technology offering high NVM memory density with 1K endurance at the lowest implementation cost to be found in...
56
11.0
NVM MTP NeoMTP in HJTC (180nm)
NeoMTP is a single-poly embedded memory technology offering high NVM memory density with 1K endurance at the lowest implementation cost to be found in...
57
11.0
NVM MTP NeoMTP in JSC (130nm)
NeoMTP is a single-poly embedded memory technology offering high NVM memory density with 1K endurance at the lowest implementation cost to be found in...
58
11.0
NVM MTP NeoMTP in SKHYNIX (180nm, 130nm)
NeoMTP is a single-poly embedded memory technology offering high NVM memory density with 1K endurance at the lowest implementation cost to be found in...
59
11.0
NVM MTP NeoMTP in SMIC (180nm, 110nm, 90nm)
NeoMTP is a single-poly embedded memory technology offering high NVM memory density with 1K endurance at the lowest implementation cost to be found in...
60
11.0
NVM MTP NeoMTP in Tower (180nm, 65nm)
NeoMTP is a single-poly embedded memory technology offering high NVM memory density with 1K endurance at the lowest implementation cost to be found in...
61
11.0
NVM MTP NeoMTP in TSMC (180nm, 90nm)
NeoMTP is a single-poly embedded memory technology offering high NVM memory density with 1K endurance at the lowest implementation cost to be found in...
62
11.0
NVM MTP NeoMTP in UMC (180nm, 160nm, 110nm, 80nm, 55nm)
NeoMTP is a single-poly embedded memory technology offering high NVM memory density with 1K endurance at the lowest implementation cost to be found in...
63
11.0
NVM OTP NeoBit in ASMC (350nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
64
11.0
NVM OTP NeoBit in CANSEMI (180nm, 110nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
65
11.0
NVM OTP NeoBit in CSMC (350nm, 250nm, 180nm, 160nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
66
11.0
NVM OTP NeoBit in DBHitek (180nm, 160nm, 130nm, 110nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
67
11.0
NVM OTP NeoBit in Fujitsu (180nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
68
11.0
NVM OTP NeoBit in GLOBALFOUNDRIES (350nm, 250nm, 180nm, 160nm, 150nm, 130nm, 110nm, 65nm, 55nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
69
11.0
NVM OTP NeoBit in Grace (180nm, 160nm, 130nm, 110nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
70
11.0
NVM OTP NeoBit in GTA (150nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
71
11.0
NVM OTP NeoBit in HJTC (180nm, 160nm, 110nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
72
11.0
NVM OTP NeoBit in Huali (55nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
73
11.0
NVM OTP NeoBit in JSC (130nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
74
11.0
NVM OTP NeoBit in MagnaChip (350nm, 180nm, 150nm, 130nm, 110nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
75
11.0
NVM OTP NeoBit in Maxchip (180nm, 160nm, 150nm, 110nm, 90nm, 80nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
76
11.0
NVM OTP NeoBit in NEXCHIP (150nm, 110nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
77
11.0
NVM OTP NeoBit in Samsung (130nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
78
11.0
NVM OTP NeoBit in SHARP (180nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
79
11.0
NVM OTP NeoBit in Silterra (180nm, 160nm, 130nm, 110nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
80
11.0
NVM OTP NeoBit in SKHYNIX (180nm, 130nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
81
11.0
NVM OTP NeoBit in SMIC (350nm, 180nm, 160nm, 130nm, 110nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
82
11.0
NVM OTP NeoBit in TSMC (350nm, 250nm, 180nm, 160nm, 130nm, 110nm, 90nm, 80nm, 55nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
83
11.0
NVM OTP NeoBit in UMC (180nm, 160nm, 130nm, 110nm, 80nm, 55nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
84
11.0
NVM OTP NeoBit in Vanguard (350nm, 250nm, 180nm, 160nm, 150nm, 110nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
85
11.0
NVM OTP NeoBit in X-FAB (250nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
86
10.0
HBM3 PHY IP at 7nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
87
10.0
GDDR6 PHY IP for 12nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
88
4.0
DDR3/ 3L/ DDR4/ LPDDR4 PHY, 22nm Technology
The DDR3, DDR3L, DDR4, and LPDDR4 Combo PHY is designed for easy integration into any System-On-Chip (SOC) and can be seamlessly connected to a third-...
89
0.3729
A bridge to convert the slave SPI interface to the master I2C interface and vice versa
The dti_spi_to_i2c is a bridge to convert the slave SPI interface to the master I2C interface and vice versa....
90
0.3729
A bridge to convert the slave SPI interface to the master UART interface and vice versa
The dti_spi_to_uart is a bridge to convert the slave SPI interface to the master UART interface and vice versa....
91
0.3729
A memory BIST solution which has been optimized for Dolphin memories
Dolphin Technology now provides a memory BIST solution which has been optimized for Dolphin memories. It supports all Dolphin memory compilers, includ...
92
0.3729
2 Ports RW Register File (2 Ports RF) Compiler with Column Redundancy Option, supports process G/LV
Memory Compilers...
93
0.3729
2 Ports RW Register File (2 Ports RF) Compiler with Column Redundancy Option, supports process GC
Memory Compilers...
94
0.3729
2 Ports RW Register File (2 Ports RF) Compiler with Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, supports process FF
Memory Compilers...
95
0.3729
2 Ports RW Register File (2 Ports RF) Compiler with Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, supports process FF
Memory Compilers...
96
0.3729
2 Ports RW Register File (2 Ports RF) Compiler with Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, supports process FF+GL/FF+LL/FFC
Memory Compilers...
97
0.3729
2 Ports RW Register File (2 Ports RF) Compiler with Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, supports process FF/FF+
Memory Compilers...
98
0.3729
2 Ports RW Register File (2 Ports RF) Compiler with Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, supports process FF/P
Memory Compilers...
99
0.3729
2 Ports RW Register File (2 Ports RF) Compiler with Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, supports process FF/P
Memory Compilers...
100
0.3729
2 Ports RW Register File (2 Ports RF) Compiler with Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, supports process FFC/FFC+
Memory Compilers...