Design & Reuse
8413 IP
6101
0.0
UCIe-S PHY for Standard Package (x16) for Automotive in TSMC (N5A)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
6102
0.0
UCIe-S PHY for Standard Package (x32) in TSMC (N3P)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
6103
0.0
CCIR 656 Decoder
The Digital Blocks DB1840 CCIR 656 Decoder IP Core decodes an ITU-R BT.656 digital video uncompressed NTSC 720x486 (525/60 Video System) and PAL 720x5...
6104
0.0
CCIR 656 Encoder
The Digital Blocks DB1830 CCIR 656 Encoder IP Core encodes 4:2:2 Y’CbCr component digital video with synchronization signals to conform to NTSC & PAL ...
6105
0.0
PCM to Class D Amplifier
The AR35S13B is a high-performance digital Class D Amplifier IP for mono speaker playback application. The amplifier converts 16-24 bits digital PCM (...
6106
0.0
ACS-AIP-DPHY-40GF-Auto - MIPI D-PHY in GlobalFoundries 40nm Automotive Process
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
6107
0.0
ACS-AIP-DPHY-40LP-RA - MIPI D-PHY TSMC 40LP Renesas- Automotive Grade
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
6108
0.0
Active frequency doubler, designed for use in the LO Path after VCO to double up the LO frequency
RFDBL03C is an active frequency doubler, designed for use in the LO Path after VCO to double up the LO frequency within the IC to feed in and drive th...
6109
0.0
Active frequency doubler, designed for use in the LO Path after VCO to double up the LO frequency
RFDBL04C is an active frequency doubler, designed for use in the LO Path after VCO to double up the LO frequency within the IC to feed in and drive th...
6110
0.0
3D GPU compatible with OpenGL ES (3D Graphics API) and OpenCL (Computing API)
DMP M3000 3D GPU IP Core adopts 3rd generation 3D graphics architecture Musashi and make remarkable progress in PPA (Power, Performance, Area) perform...
6111
0.0
3D GPU supporting OpenGL ES2.0 capability
The DMP ant300 is the world’s smallest class 3D graphics IP core supporting OpenGL ES2.0 capability. It is the premiere solution for popular ASIC/ASSP...
6112
0.0
2D Graphics IP Core
DMP K3000 2D GPU IP Core offers the most powerful rendering performance in the industry, with a minimum area solution. You will witness blazing font a...
6113
0.0
2D Graphics Rendering Engine
Digital Blocks 2D Graphics Hardware Accelerator Verilog IP Cores consists of the DB9200AXI4, DB9200AXI, DB9200AHB, and DB9200AVLN. The DB9200 2D Graph...
6114
0.0
MD5 Hashing Core
The es1005 hash fully implements the MD5 (Message Digest Algorithm RFC 1321). The core can be used for data authentication in digital broadband, wire...
6115
0.0
VDC-M (VESA Display Compression-M) Decoder
The Rambus VESA VDC-M 1.2 Decoder IP Core (formerly from Hardent) implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 decoder to deliv...
6116
0.0
VDC-M (VESA Display Compression-M) Encoder
The Rambus VESA VDC-M 1.2 Encoder IP Core (formerly from Hardent) implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 encoder to deliv...
6117
0.0
HDCP 2.0 Encryption Suite
HDCP Suite consists of hardware and software components implementing the HDCP 2.0 protocol. The hardware components are fully synchronous and availabl...
6118
0.0
HDCP Encryption-Decryption Engine
The Trilinear Technologies High-bandwidth Digital Content Protection (HDCP) Encryption-Decryption Engine IP core allows system designers to accelerate...
6119
0.0
HDCP Engine
The EIP-116 High-bandwidth Digital Content Protection Control Path module provides the required technology for implementing all the secure access, cry...
6120
0.0
GDDR6 Memory PHY for TSMC N5P
Designed for high performance and low latency in AI/ML, graphics and networking The latest, the Denali PHY IP for GDDR6, is comprised of architectura...
6121
0.0
GDDR6 Memory PHY for TSMC N7
Designed for high performance and low latency in AI/ML, graphics and networking The latest, the Denali PHY IP for GDDR6, is comprised of architectura...
6122
0.0
GDDR6 PHY for TSMC N6
High-performance IP for graphics, AI/ML, and automotive products The latest, the Denali PHY IP for GDDR6, is comprised of architectural improvements ...
6123
0.0
GDDR7 Memory PHY for TSMC N3P
High performance for graphics, AI, and automotive products The Cadence IP solution for GDDR7 consists of high-performance hardened PHY, serving hig...
6124
0.0
GDDR7 Memory PHY for TSMC N4P
High performance for graphics, AI, and automotive products The Cadence IP solution for GDDR7 consists of high-performance hardened PHY, serving high-...
6125
0.0
GDDR7 Memory PHY for TSMC N5P
High performance for graphics, AI, and automotive products The Cadence IP solution for GDDR7 consists of high-performance hardened PHY, serving high-...
6126
0.0
SDIO HOST VMM based Verification IP
The Secure Digital Input Output (SDIO) interface is a card interface defined to connect a SD Host Controller with four different types of cards, namel...
6127
0.0
3DIO PHY IP for TSMC N5
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...
6128
0.0
HDMI 2.1 Forward Error Correction (FEC) Receiver
The HDMI Forward Error Correction (FEC) Receiver IP Core implements Reed-Solomon FEC and symbol de-interleaving/de-mapping as specified by the HDMI 2....
6129
0.0
HDMI 2.1 Forward Error Correction (FEC) Transmitter
The HDMI Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol mapping/interleaving as specified by the HDMI 2.1 ...
6130
0.0
HDMI 2.1/DisplayPort 2.1 TX PHY in Samsung (SF4A) for Automotive
The Synopsys HDMI 2.1 TX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide th...
6131
0.0
HDMI 2.1/DisplayPort 2.1 TX PHY in Samsung (SF5A)
The Synopsys HDMI 2.1 TX Controller and PHY IP solutions,compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the...
6132
0.0
HDMI 2.1/DisplayPort eDP 1.4 TX PHY in TSMC (N6C, N4C)
The Synopsys HDMI 2.1 TX Controller and PHY IP solutions,compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the...
6133
0.0
UDP/IP Hardware Protocol Stack - 100G
The Digital Blocks DB-UDP-IP-100GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 100 GbE n...
6134
0.0
UDP/IP Hardware Protocol Stack - 10G
The Digital Blocks DB-UDP-IP-10GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 10 GbE net...
6135
0.0
UDP/IP Hardware Protocol Stack - 1G
The Digital Blocks DB-UDP-IP-1GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 10 GbE netw...
6136
0.0
UDP/IP Hardware Protocol Stack - 25G
The Digital Blocks DB-UDP-IP-25GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 25 GbE net...
6137
0.0
UDP/IP Hardware Protocol Stack - 40G
The Digital Blocks DB-UDP-IP-40GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 50 GbE net...
6138
0.0
UDP/IP Hardware Protocol Stack - 50G
The Digital Blocks DB-UDP-IP-50GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 50 GbE net...
6139
0.0
LDPC for 5G DVBS2 802.11
Encoder: - Every H-matrix (out of 102, 51 for BG1, and 51 for BG2 in 5G) has its encoder, which is just a bunch of XOR gates and co...
6140
0.0
DDR2 SDRAM VIP
Double-Data-Rate-Two Synchronous Dynamic Random Access Memory (DDR2 SDRAM) is the memory technology used for high speed data transfer. This class of m...
6141
0.0
DDR3 Memory Controller
Rambus’s DDR3 Controller Core offered by Rambus is designed for use in applications requiring high memory throughput, high clock rates and full progra...
6142
0.0
DDR3 PHY
Designed for server, networking, computing and consumer applications, our DDR4 multi-modal memory PHY is optimized for performance The DDR4 multi-m...
6143
0.0
DDR3/3L/DDR4/LPDDR4 PHY
The DDR3, DDR3L, DDR4, and LPDDR4 Combo PHY is designed for easy integration into any System-On-Chip (SOC) and can be seamlessly connected to a third-...
6144
0.0
DDR4 Memory Controller
Rambus DDR4 Controller Core from Rambus is designed for use in applications requiring high memory throughput, high clock rates and full programmabilit...
6145
0.0
DDR4 Multi-modal PHY
Designed for server, networking, computing and consumer applications, our DDR4 multi-modal memory PHY is optimized for performance The DDR4 multi-m...
6146
0.0
DDR4 PHY
Designed for server, networking, computing and consumer applications, our DDR4 multi-modal memory PHY is optimized for performance The DDR4 multi-m...
6147
0.0
DDR4 PHY, 16nm/12nm
The DDR4 PHY is designed for easy integration into any System-On-Chip (SOC) and can be seamlessly connected with a third-party DFI-compliant DDR4 memo...
6148
0.0
DDR4/3 Memory PHY for TSMC N7
Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area The latest, the Denali ...
6149
0.0
DDR5 Memory PHY for Samsung SF5A Automotive
Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area The latest, the DDR5 PH...
6150
0.0
DDR5 Memory PHY for TSMC N3P
Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area The latest, the DDR5 PH...