Design & Reuse
3739 IP
2501
0.118
Two Port Register File Compiler IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process synchronous Two Port (1R1W) Register File SRAM memory compiler....
2502
0.118
Two Port Register File Compiler IP, UMC 0.25um process
UMC 0.25um Logic process synchronous Two Port Register File compiler....
2503
0.118
Two Port Register File Compiler IP, UMC 0.25um process
UMC 0.25um Logic process synchronous low density Low Power Two Port (1R1W) SRAM memory compiler....
2504
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous low density Low Power Two Port (1R1W) SRAM memory compiler....
2505
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous high density Two Port (1R1W) SRAM memory compiler....
2506
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous high density Two Port (1R1W) SRAM memory compiler....
2507
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous low density Low Power Two Port (1R1W) SRAM memory compiler....
2508
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous low density Low Power Two Port (1R1W) SRAM memory compiler....
2509
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous high density Two Port (1R1W) SRAM memory compiler....
2510
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous high density Two Port (1R1W) SRAM memory compiler....
2511
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous low density Low Power Two Port (1R1W) SRAM memory compiler....
2512
0.118
Two Port Register File Compiler IP, UMC 28nm HLP process
UMC 28nm HLP/ Low-K Two Port Register File compiler....
2513
0.118
Two Port Register File Compiler IP, UMC 28nm HLP process
UMC 28nm HLP peripheral LVT Two Port Register File memory compiler....
2514
0.118
Two Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP/LVT process, Two Port Register File with LVT....
2515
0.118
Two Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP Two Port Register File with Sleep/Retention/Nap mode feature....
2516
0.118
Two Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP/RVT Low-K Logic Two Port Register File memory compiler....
2517
0.118
Two Port Register File Compiler IP, UMC 55nm LP process
UMC 55nm LP/ Low-K process PG Two Port Register File compiler....
2518
0.118
Two Port Register File Compiler IP, UMC 55nm LP process
UMC 55nm LP Logic process Synchronous Two Port Register File memory compiler....
2519
0.118
Two Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm SP/RVT and HVT Low-K Logic process synchronous ultra high density/6T cell Two Port Register File memory compiler....
2520
0.118
Two Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm SP Low-K Logic process synchronous Two Port Register File memory compiler....
2521
0.118
Two Port Register File Compiler IP, UMC 65nm LL process
UMC 65nm LL/RVT Low-K Logic process synchronous high density Two Port Register File SRAM memory compiler....
2522
0.118
Two Port Register File Compiler IP, UMC 65nm SP process
UMC 0.65um SP/RVT Low-K Logic process synchronous Two Port Register File memory compiler....
2523
0.118
Two Port Register File Compiler IP, UMC 90nm LL process
UMC 90nm LL/RVT Synchronous high density Two Port Register File memory compiler....
2524
0.118
Two Port Register File Compiler IP, UMC 90nm SP process
UMC 90nm Standard Performance Low-K process Two Port SRAM Register File compiler....
2525
0.118
Two Port Register File Compiler IP, UMC 90nm SP process
UMC 90nm SP Logic Low-K process synchronous Two Port (1R1W) Register File SRAM memory compiler....
2526
0.118
FXAFE030HH0L is an Analog Front End IP for image processing applications. FXAFE030HH0L is fabricated in UMC 40 nm logic LP/HVT Low-K process to implement a signal processing solution for scanners, video and imaging applications. _x005F_x005F_x005F_x000D_
FXAFE030HH0L is an Analog Front End IP for image processing applications. FXAFE030HH0L is fabricated in UMC 40 nm logic LP/HVT Low-K process to implem...
2527
0.118
AXI Bus Controller IP, Bus Controller, Soft IP
Register Slice Controller with AXI bus interface....
2528
0.118
AXI system Peripheral IP, AXI Bus System Interconnect, Soft IP
AXI bus interconnect....
2529
0.118
AXI system Peripheral IP, AXI to AXI Bridge, Soft IP
AMBA AXI to AXI Bridge....
2530
0.118
AXI system Peripheral IP, AXI/APB host bridge, Soft IP
AXI/APB host bridge controller....
2531
0.118
AXI system Peripheral IP, Cache Controller, L2 Cache, Soft IP
L2 cache controller with AXI interface....
2532
0.118
AXI system Peripheral IP, DMA controller for AXI master port and slave port (32 - bit, 64 - bit and 128 - bit), 8 channels DMA, Soft IP
DMA controller with AXI interface....
2533
0.118
AXI system Peripheral IP, Interrupt Controller, Soft IP
Generic Interrupt Controller with AXI interface. Faraday's FTINTC030 Generic interrupt controller supports software generated interrupt, private perip...
2534
0.118
TypeC CC channel for USBPD ; UMC 40NM LP Low-K process.
TypeC CC channel for USBPD ; UMC 40NM LP Low-K process....
2535
0.118
1~50V/V low offset PGA for SAR-ADC ; UMC 0.18um Mixed-Mode PROCESS
1~50V/V low offset PGA for SAR-ADC ; UMC 0.18um Mixed-Mode PROCESS...
2536
0.0
8-bit micro-controller high speed 4clk/machine cycle architecture256 bytes of on-chip Data RAM,Three 16-bit timer/countersTwo 16-bit dptr
8-bit micro-controller high speed 4clk/machine cycle architecture256 bytes of on-chip Data RAM,Three 16-bit timer/countersTwo 16-bit dptr...
2537
0.0
Faraday - SoC Design Services
The increasing complexity, interface, and functionality of SoCs have brought out much more challenges than the traditional chip implementation. To mak...
2538
0.0
Vector Floating-point coprocessor based on ARM VFPv2 Instruction Set Architecture for FA626TE 32-bit RISC CPU
Vector Floating-point coprocessor based on ARM VFPv2 Instruction Set Architecture for FA626TE 32-bit RISC CPU...
2539
0.0
Single Port SRAM Compiler IP, 4.0um2 bit cells, Synchronous high density, UMC 0.18um HV process
UMC 0.18um high voltage 1.8V process synchronous high density Single Port SRAM memory compiler....
2540
0.0
Power on Reset IP, Input: 1.2V, UMC 0.13um HS/FSG process
Vrr=0.8V Vfr=0.65V, VCC=1.2V, Ivcc=12.7uA, HS process with B-type IO., Power On Reset, UMC 0.13um HS/FSG Logic process....
2541
0.0
Specialty SSTL IO IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process true 2.5V SSTL2 IO cells....
2542
0.0
USB Type-C and Power deliver Controller
USB Type-C and Power deliver Controller...
2543
0.0
Two Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP/ Low-K process, Two Port Register File memory compiler....
2544
130.0
LPDDR6, LPDDR5X Combo PHY & Controller
INNOSILICON™ introduces its LPDDR6/5X PHY and Controller IP, purpose-built for the AI era’s high-performance chip design needs. This solution is fully...
2545
100.0
1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
eTopus designs ultra-high speed mixed-signal semiconductor IP solutions for high-performance computing and data center applications. Our 1-56/112Gbps ...
2546
100.0
400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
...
2547
100.0
56G Serdes in 7nm bundled with PCie Gen 5 controller IP
New IP for value conscious designers....
2548
100.0
PCIe 5.0 PHY & Controller
The Innosilicon Gen1/2/3/4/5 PCI Express Controller provides a PCI Express Root Complex (RC) and Endpoint (EP) application. It’s a high performance, h...
2549
100.0
PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
Multiprotocol low latency, low power SERDES IP....
2550
100.0
The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.
SuperFlash® is SST’s patented and proprietary NOR flash technology. With 80B+ devices shipped, SuperFlash is the non-volatile memory of choice for emb...