Design & Reuse
3897 IP
151
0.0
LPDDR3/2 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR3/2 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SD...
152
0.0
LPDDR3/2/DDR3/3L Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR2/3/DDR3/3L COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compa...
153
0.0
LPDDR3/2/DDR3/3L/2 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR3/2/DDR3/3L/2 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC com...
154
0.0
LPDDR4X, LPDDR4, DDR4, LPDDR3 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR4/4X/DDR4/LPDDR3 PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compat...
155
0.0
LPDDR4X/4/3/DDR4/3/3L PHY + Controller
INNOSILICON™ LPDDR4X/4/3/DDR4/3/3L Combo IP is a customizable Mixed-Signal DDR memory interface suite. The Combo IP provides turnkey physical interfac...
156
0.0
MRDIMM DDR5 & DDR5/4 PHY & Controller
INNOSILICON™ DDR5 IP includes the MRDIMM DDR5 PHY and DDR5/4 Combo PHY and corresponding controllers for ICs requiring access to JEDEC compatible SDRA...
157
0.0
Process/Voltage/ Temperature Sensor
INNOSILICON™ PVT Sensor IP is designed for on-chip monitoring of processes, voltage, and temperature variations. It is a critical component in modern ...
158
0.0
HSIC PHY
The Innosilicon HSIC PHY is fully compliant with the High-Speed Inter-Chip Supplement to the USB 2.0 Specification. By stripping off all the legacy US...
159
0.0
PSRAM PHY
The INNOSILICON DDR IPTM Mixed-Signal PSRAM PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible PSRAM devic...
160
0.0
PSRAM/RPC PHY & Controller
INNOSILICON™ PSRAM IP consists of a configurable PHY and RPC PHY and a controller. It provides the physical interface solutions for ICs requiring acce...
161
0.0
LTE UE PHY layer
The PHY baseband covers all Synchronization Signals, downlink and uplink Physical Channels, libraries, algorithms integrated with cross-functional log...
162
0.0
LTE UE Protocol Stack HW (Arm, Cortex A8)
Mymo offers 3GPP LTE Release-9 UE FDD and TDD UE Protocol Stack on Arm hardware . The Integrated solution of MAC-RLC-PDCP-RRC-NAS-TCP-IP with several ...
163
0.0
LTE UE Protocol Stack Software
Mymo offers 3GPP LTE Release-9 UE FDD and TDD UE Protocol Stack software. The software is in ANSI C ported at RT-Linux kernel level ideally suited for...
164
0.0
Successive Approximation ADC_2M10b
Innosilicon SARADC IP is a small-sized, low power analog to digital converter with input channels. The converter is a charge-redistribution successive...
165
0.0
Successive Approximation ADC_2M12b
Innosilicon SAR-ADC IP is a small-size, low power analog to digital converter. The converter is a charge-redistribution successive approximation ADC. ...
166
0.0
Successive Approximation ADC_3M10b
Innosilicon SARADC IP is a small-sized, low power analog to digital converter with input channel and Standard I/O multiplexed. The converter is a char...
167
0.0
Audio Codec
INNOSILICON™ Audio Codec IP is a low power, high resolution, stereo audio solution which leverages Sigma-Delta noise-shaping technology. The ADC, DAC,...
168
0.0
PUF Security
A physical unclonable function, or PUF, is a "digital fingerprint" that serves as a unique identity for a semiconductor device such as a microprocesso...
169
0.0
eUSB2 PHY
The industry’s most advanced process nodes do not support 3.3V signaling and 5V tolerance as required by the USB 2.0 specification. 3.3V signaling was...
170
0.0
LVDS RX PHY & Controller
Innosilicon LVDS implements LVDS TIA/EIA protocol. It specifies a low-voltage point-to-point signal interface, which uses a differential driver connec...
171
0.0
LVDS TX Combo TTL PHY
Innosilicon LVDS implements LVDS TIA/EIA protocol. Normally, Innosilicon LVDS contains four 7-bit parallel-load serial-out shift registers, a 7X clock...
172
0.0
LVDS TX PHY & Controller
Innosilicon LVDS implements LVDS TIA/EIA protocol. It specifies a low-voltage point-to-point signal interface, which uses a differential driver connec...
173
0.0
LVDS/TTL PHY & Controller
INNOSILICON™ LVDS/TTL IP implements the LVDS TIA/EIA protocol, providing a low-voltage, high-speed point-to-point signal interface. It supports either...
174
0.0
Type-C PHY
Innosilicon Type-C IP is composed of the physical layer and the PHY logic. The physical layer contains 4 data channels, an AUX channel and bias circui...
175
200.0
Post-Quantum Cryptography - xQlave® PQC ML-KEM (Kyber)
In a world where advances in quantum computing threaten traditional cryptographic systems, Xiphera’s xQlave® ML-KEM (Kyber) Key Encapsulation Mechanis...
176
105.0
CME IoT platform
Sensor-Mate (sensing node)Long distance wireless communication (920MHz)Sensor-Gateway (Aggregator)920MHz wireless module (CM Engineering proprietary)G...
177
100.0
MACsec - Extreme-speed - Security Protocol
MACsec is a point-to-point protocol located on layer two (Data Link) of the OSI model. Xiphera's comprehensive MACsec solution portfolio safeguards th...
178
100.0
Post-Quantum Cryptography - nQrux® Secure Boot - Quantum-Secure Authenticated Boot (PQC)
nQrux® Secure Boot enhances system security by enabling quantum-secure authenticated boot, crucial for verifying the authenticity and integrity of bin...
179
100.0
Post-Quantum Cryptography - xQlave® PQC ML-DSA (Dilithium)
The xQlave® ML-DSA (Dilithium) Digital Signature Algorithm IP core secures critical infrastructures and operations against the threat of quantum compu...
180
51.0
TLS 1.3 - Security Protocol
Transport Layer Security (TLS) is a cryptographic protocol used for building a secure connection between a client and a server over the Internet. A ha...
181
51.0
True Random Number Generator (TRNG)
The TRNG IP core establishes a benchmark for hardware-based security in cryptographic systems, by generating high-entropy, true random numbers essenti...
182
50.0
MAXVY Technologies
MAXVY is a fast growing fabless semiconductor company which is currently engaged in the fields of RTL design and Verification IP Solutions. We offe...
183
50.0
AES - GCM - Extreme-speed variant
XIP1113E is a an extreme-speed IP core implementing the Advanced Encryption Standard (AES) in Galois Counter Mode (GCM). AES-GCM is a widely used cryp...
184
50.0
IPsec - Security Protocol
IPsec (Internet Protocol Security) is a widely implemented protocol to secure communications across the Internet. Xiphera’s IPsec core enhances secure...
185
48.0
nQrux® Crypto Module
Xiphera’s nQrux® Crypto Module IP core provides a comprehensive security platform that allows for customisation of top-notch cryptographic services, s...
186
43.0
Elliptic Curve Cryptography (ECC) Accelerator
The high-speed ECC Accelerator reaches to more than a thousand operations per second in a modern FPGA or ASIC. Furthermore, it covers all NIST P curve...
187
10.0
MIPI DSI-2 Transmitter Interface IP
MIPI DSI-2 (Display Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile dev...
188
8.0
MIPI I3C Verification IP with IBI feature enabled
The Maxvy's MIPI-I3C VIP provides configurable option to select I3C master/secondary master/slave based on the MIPI I3C DUT function as per user speci...
189
8.0
Universal Chiplet Interconnect Express (UCIe) Verification IP
MAXVY UCIe VIP , a state-of-the-art solution that offers a comprehensive set of features and capabilities to ensure the quality and performance of you...
190
5.0
MIPI I3C Master RISC-V based subsystem
RISC-V based MAXVY MIPI I3C master interface has been developed to ease sensor system design architectures in mobile wireless products by providing a ...
191
5.0
MIPI SPMI Target Controller
The System Power Management Interface is a two wire interface that connects the integrated power controller (PC) of a System-on-Chip (SoC) processor s...
192
5.0
MIPI-I3C Combo Host and Target interface controller IP for Sensor and Peripheral connection
The MIPI I3C (Improved Inter Integrated circuit) is a two wire bidirectional Serial Bus for sensor communication. The MIPI I3C interface has been ...
193
5.0
MIPI-I3C Combo IP Host/Target HDR-DDR compliance with Spec v1.1.1
MIPI I3C(Improved Inter Integrated Circuit) is a two-wire bidirectional serial Bus for sensors communication. The MIPI I3C interface has been develope...
194
4.0
32 bit 8Ksps sigma delta ADC for Seismic Precision application in TSMC 180nm
32-bit delta sigma analog-to-digital converter (ADC) containing a low noise programmable gain amplifier (PGA) and 2 channel input multiplexers. This A...
195
4.0
12b 5Msps ADC for microcontroller business in UMC 40nm
AD12BSAR5M40LP is a 12-bit Successive Approximation Analog-to-Digital Converter (ADC) that operates up to 5MS/s. The ADC has excellent linearity with ...
196
4.0
12b, 5Gsps, 0.9/1.8V Self Calibrating, Current steering DAC for 5G in TSMC 28nm
DA12B5000M28HPC is high performance 12b current steering DAC that supports data rate up-to 5Gsps. DAC core consists of a current source matrix with qu...
197
4.0
12b, 5Gsps, 0.9/1.8V Self Calibrating, Current steering DAC for 5G in UMC 28nm
DA12CS5GU28HPCP is high performance 12b current steering DAC that supports data rate up-to 5Gsps. DAC core consists of a current source matrix with qu...
198
4.0
14b, 1.3Gsps, 40MHz BW ADC in TSMC 28nm
AD14B40M28HPC is a wide band continuous time sigma delta ADC with -80dBc of dynamic range in 40Mhz bandwidth. The ADC comprises of a continuous time s...
199
4.0
14b, 2Gsps, Self-Calibrating Current Steering IQDAC in samsung 8nm for 5G & WIFI6
DAIQ14CS2G08NLL is high performance 14b current steering IQDAC that supports data rate up-to 2Gsps. Each DAC core consists of a current source matrix ...
200
4.0
14b, 3.2Gsps, 75MHz BW ADC for RADAR in 28nm
AD14B75M28HPC is a wide band continuous time sigma delta ADC with -80dBc of dynamic range in 75Mhz bandwidth. The ADC comprises of a continuous time s...