Design & Reuse
4331 IP
551
2.0
QSPI - DQSPI - Serial Peripheral Interface - Master/Slave with single, dual and quad SPI Bus support -
The DQSPI is a revolutionary quad SPI designed to offer the fastest operations available for any serial SPI memory. It is flexible enough to interface...
552
2.0
Pulse Per Second Slave (PPS) core
NetTimeLogic’s PPS Slave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to a Pulse per Second input...
553
1.0
8051 - DQ8051 - Revolutionary Quad-Pipelined Ultra High Performance Microcontroller
The DQ8051 is an ultra high performance, speed optimized soft core of a single-chip 8-bit embedded controller, designed to operate with fast (typicall...
554
1.0
2692 - D2692 - Dual UART
The D26C92 is a Dual UART Core software compatible with the SC26C92, SCC2692 and SCN2681 with added features and deeper FIFOs. It contains: 8 charac...
555
1.0
Radio Clock (DCF77) Master core
NetTimeLogic’s DCF Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize other nodes via DCF signal...
556
1.0
Radio Clock (DCF77) Slave core
NetTimeLogic’s DCFSlave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to a DCF signal encoded as P...
557
1.0
Maximum normalised correlation core
The eSi-MNC core provides the control and data plane interfaces to a Maximum Normalised Correlation module. The signal processing in the core consist...
558
1.0
VCC Detector to detects 1.2V core supply, output 3.3V digital signal
The present IP is a VCC Detector (VDT) circuit with normal operating voltage ranging from 1.08V ~1.32V. It first detects the core supply and then give...
559
1.0
Real Time Clock (RTC) Master core
NetTimeLogic’s RTC Master Clock is a full hardware (FPGA) only implementation of a synchronization core allowing to read and write a I2C Realtime Cloc...
560
1.0
DES/TDES core
The eSi-DES block performs encryption and decryption of 64-bit words using the DES (Data Encryption Standard) and TDEA (Triple DES Encryption Algorith...
561
1.0
AGC Control and data plane core
The eSi-AGC core provides the control and data plane interfaces to an AGC module. The signal processing in the core consists of a sliding energy est...
562
1.0
SHA256 & SHA224 core
The eSi-SHA256 core is an easy to use SHA hash accelerator peripheral for both SHA256 and SHA224. This is a cryptographic hash function designed by t...
563
1.0
High-Performance, Configurable, 8-bit 8051 Microcontroller Core
This 8051 IP core implements a range of fast, 8-bit, 8051-compatible microcontrollers that execute the MCS®51 instruction set. The R8051XC2 IP core...
564
1.0
Digital Down Converter core
The eSi-DDC is a Digital Down Converter combining a Digital Frequency Synthesizer (DDS) with a Digital Mixer. The DDS is implemented in a resource ef...
565
1.0
Time aligned Frequency Generator core
The Frequency Generator from NetTimeLogic is a clock aligned frequency generator allowing any frequency to be generated between 1Hz and 10MHz adjustab...
566
1.0
Time aligned Signal Generator core
The Signal Generator from NetTimeLogic is a clock aligned pulse and pattern (PWM) generator with nanosecond resolution (second and nanosecond format)....
567
1.0
Time aligned Signal Timestamper core
The Signal Timestamper from NetTimeLogic is a timestamper with nanosecond resolution (second and nanosecond format). It uses NetTimeLogic's Adjustable...
568
1.0
NMEA Time of Day (ToD) Master core
NetTimeLogic’s Time Of Day (ToD) Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize a Time of Da...
569
1.0
Core Voltage Regulator
The OT1104 is a CMOS 75mA on-chip core voltage regulator designed for use when a pin for an external decoupling capacitor is not available. A source...
570
1.0
IRIG-B Master core
NetTimeLogic’s IRIG Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize other nodes via IRIG-B007...
571
1.0
PSMBUS - DPSMBUS - SMBUS & PMBUS Master/Slave controller
The DPSMBUS is a fully-featured module based on the I2C protocol, which supports SMBus and PMBus functionalities. It can operate as a DPSMBUSM – Ma...
572
1.0
Pulse Per Second (PPS) Clock to PPS core
NetTimeLogic’s PPS Clock to PPS core is a full hardware (FPGA) only implementation of a PPS generator out of a clock of configurable frequency, it is ...
573
1.0
Pulse Per Second Master (PPS) core
NetTimeLogic’s PPS Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize other nodes to a Pulse per...
574
1.0
Super-Fast 8051 Microcontroller Core with Configurable Features and Peripherals
The S8051XC3 IP core implements a high-performance, low-energy, 8-bit microcontroller that executes the MCS®51 instruction set and includes a configur...
575
0.118
HJTC 0.11um eFlash Process Generic Core Cell Library (porting from FSR0K_D)
HJTC 0.11um eFlash Process Generic Core Cell Library (porting from FSR0K_D)...
576
0.118
UMC 0.11um HS/AL Logic Process High Density Version MPCA core cell library with mini programming layer from V1 to M4
UMC 0.11um HS/AL Logic Process High Density Version MPCA core cell library with mini programming layer from V1 to M4...
577
0.118
UMC 0.11um HS/FSG Logic Process high density MPCA core cell library with minimum Via1 to M4 programming
UMC 0.11um HS/FSG Logic Process high density MPCA core cell library with minimum Via1 to M4 programming...
578
0.118
UMC 0.13um LL/FSG Logic Process Metal1 Start ECO core cell library
UMC 0.13um LL/FSG Logic Process Metal1 Start ECO core cell library...
579
0.118
UMC 0.13um SP/FSG Logic Process Metal1 Start ECO core cell library
UMC 0.13um SP/FSG Logic Process Metal1 Start ECO core cell library...
580
0.118
UMC 0.18um Generic process MPCA core cell library
UMC 0.18um Generic process MPCA core cell library...
581
0.118
UMC 0.18um GII Logic Process 3.3V core cell library
UMC 0.18um GII Logic Process 3.3V core cell library...
582
0.118
UMC 0.3um HV process, M1-start ECO (engineering change order) core cell library
UMC 0.3um HV process, M1-start ECO (engineering change order) core cell library...
583
0.118
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 12-track Standard Generic core cell library (C30)
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 12-track Standard Generic core cell library (C30)...
584
0.118
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C30)
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C30)...
585
0.118
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C35)
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C35)...
586
0.118
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C40)
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C40)...
587
0.118
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C30)
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C30)...
588
0.118
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C35)
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C35)...
589
0.118
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C40)
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C40)...
590
0.118
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 12-track Standard Generic core cell library (C30)
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 12-track Standard Generic core cell library (C30)...
591
0.118
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 12-track Standard Generic core cell library (C40)
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 12-track Standard Generic core cell library (C40)...
592
0.118
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C30)
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C30)...
593
0.118
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C35)
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C35)...
594
0.118
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C40)
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C40)...
595
0.118
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C30)
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C30)...
596
0.118
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C35)
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C35)...
597
0.118
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C40)
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 9-track Generic Core cell library enhanced for routing (C40)...
598
0.118
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 1.8V device RTC Core Library
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 1.8V device RTC Core Library...
599
0.118
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C30)
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C30)...
600
0.118
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C35)
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track Generic Core cell library enhanced for routing (C35)...