5001 2.0

Gigabit Ethernet 802.3 MAC - Media Access Controller The Gigabit Ethernet Media Access Controller with AHB Interface IP core is compliant to the Ethernet/IEEE 802.3-2008 standard. The Gigabit Ethernet - ...

5002 2.0

High performance 1.8V reference current and voltage generator The ODT-REF-16FFCT-SV1P8 is a high-performance reference current and voltage generator. The block incorporates a proprietary architecture to achieve h...

5003 2.0

Single Channel UART with Scalable Rx-FIFO Universal asynchronous receiver and transmitter (UART) using the RS232 protocol are often used to connect peripheral devices to a central controller. ...

5004 2.0

MIPI D-PHY UMC 65LL Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...

5005 2.0

MIPI D-PHY - UMC 55eHV Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...

5006 2.0

MIPI D-PHY Digital Front-End for FPGA Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...

5007 2.0

MIPI D-PHY Global Foundries 65LPe Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...

5008 2.0

MIPI D-PHY SMIC 40nm Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...

5009 2.0

MIPI D-PHY TSMC 40LP eDRAM Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...

5010 2.0

MIPI D-PHY TSMC 40LP Renesas- Automotive Grade Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...

5011 2.0

MIPI M-PHY - UMC 40nm MIPI M-PHY Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A M-PHY config...

5012 2.0

eMMC 5.1 HS400 PHY and I/O Pads in TSMC 16FF-NS Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...

5013 2.0

FortifyIQ AES-SX-GCM-XTS Secure Core: High-Performance AES Encryption Core with GCM/XTS Support and Advanced SCA/FI Protection FortifyIQ’s High-Performance AES Encryption Core is a fast, encryption-only hardware accelerator built for systems that demand secure and authenticate...

5014 2.0

FortifyIQ AES-SX-full Secure Core: High-Performance AES Encryption/Decryption Core with Advanced SCA/FI Protection FortifyIQ’s High-Performance AES IP core delivers fast, secure AES-128/256 encryption and decryption for systems requiring high throughput and certifi...

5015 2.0

FortifyIQ AES-SX-ULP-full Secure Core: Ultra-Low-Power AES Core with Proven SCA Protection for Constrained Devices (SCA/DPA/FIA resistant) FortifyIQ’s Ultra-Low-Power AES IP core is a compact encryption engine optimized for deeply embedded and battery-powered systems where minimizing ener...

5016 2.0

FortifyIQ AES-SX-ULP-full Secure Core: High-Performance, Ultra Low-Power AES Encryption Core with Full Mode Support and Formally Proven SCA Protection (SCA/DPA/FIA resistant) FortifyIQ’s High-Throughput, low-power consumption AES IP core delivers AES-128/256 encryption-only with full support for ECB, CBC, CTR, GCM, and XTS ...

5017 2.0

FortifyIQ AES-SX-ULP-full Secure Core: High-Performance/Ultra Low Power AES Encryption Core with Full Mode Support and Formally Proven SCA Protection (SCA/DPA/FIA resistant) FortifyIQ’s Ultra Low Power, High-Throughput AES IP core delivers AES-128/256 encryption-only with full support for ECB, CBC, CTR, GCM, and XTS modes,...

5018 2.0

FortifyIQ AES-SX-ULP-full Secure Core: Ultra-Low-Power AES Encryption Core with Full Mode Support and Formally Proven SCA Protection (SCA/DPA/FIA resistant) FortifyIQ’s Low-Energy AES IP core delivers AES-128/256 encryption-only with support for all major modes, including ECB, CBC, CTR, GCM, and XTS, while...

5019 2.0

FortifyIQ Balanced AES Core with Multi-Mode Support and Advanced SCA/FI Protection FortifyIQ’s Balanced AES IP core is a compact yet capable cryptographic accelerator designed for embedded systems with moderate performance and resour...

5020 2.0

FortifyIQ High-Throughput AES Core with Advanced SCA/FI Protection for Performance-Critical Systems FortifyIQ’s High-Performance AES IP core is a fast, silicon-proven cryptographic engine designed for systems with demanding encryption workloads. Buil...

5021 2.0

Super Speed USB 3.0 Extensible Host Controller xHCI ...

5022 2.0

TVM - Temperature/Voltage Monitor in 28nm CMOS The ODT-TVM-ULP-001C-28 is an ultra-low power temperature and voltage monitor designed in a standard 28nm CMOS process. The IP operates over the entir...

5023 2.0

TVM - Temperature/Voltage Monitor in 40nm CMOS The ODT-TVM-ULP-001C-40 is an ultra-low power temperature and voltage monitor designed in a standard 40nm CMOS process. The IP operates over the entir...

5024 1.0

1.2V Low Voltage Detector (LVD), Fujitsu 90nm The AR22F01 is a mass-production proven low voltage detector (LVD) IP. The LVD monitors analog pad power supply levels to prevent possible damage of c...

5025 1.0

I2C Bus Interface The serial controller interface (Single Master) core uses a two-wire bus for communicating between integrated circuits or standard peripherals like sm...

5026 1.0

I2C Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus) The Digital Blocks DB-I2C-MS-AXI Controller IP Core interfaces a microprocessor via the AXI system Interconnect Fabric to an I2C Bus. The I2C is a t...

5027 1.0

14-bit, 600 MSPS Ultra Low Power ADC in 28nm CMOS The ODT-ADP-14B600M-28 is a low power high speed pipelined ADC designed in a 28nm standard CMOS process, implemented using Omni Design's groundbreaki...

5028 1.0

Serial Controller Interface Inicore’s iniSCI Slave is a synthesizable, flexible, and structured VHDL implementation of a Serial Controller Interface (SCI) that uses a two-wire bu...

5029 1.0

GF L013HP 130nm Clock Generator PLL - 105MHz-525MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

5030 1.0

GF L013HP 130nm Clock Generator PLL - 210MHz-1050MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

5031 1.0

GF L013HP 130nm Clock Generator PLL - 420MHz-2100MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

5032 1.0

GF L013HP 130nm DDR DLL - 120MHz-600MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

5033 1.0

GF L013HP 130nm DDR DLL - 189MHz-945MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

5034 1.0

GF L013HP 130nm DDR DLL - 90MHz-450MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

5035 1.0

GF L013HP 130nm Deskew PLL - 105MHz-525MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

5036 1.0

GF L013HP 130nm Deskew PLL - 210MHz-1050MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

5037 1.0

GF L013HP 130nm Deskew PLL - 420MHz-2100MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

5038 1.0

GF L013HP 130nm General Purpose PLL - 210MHz-1050MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

5039 1.0

GF L013HP 130nm Spread Spectrum PLL - 105MHz-525MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

5040 1.0

GF L013HP 130nm Spread Spectrum PLL - 210MHz-1050MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

5041 1.0

GF L013HP 130nm Spread Spectrum PLL - 420MHz-2100MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

5042 1.0

GF L013LP 130nm Clock Generator PLL - 180MHz-900MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

5043 1.0

GF L013LP 130nm Clock Generator PLL - 45MHz-225MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

5044 1.0

GF L013LP 130nm Clock Generator PLL - 90MHz-450MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

5045 1.0

GF L013LP 130nm DDR DLL - 39MHz-195MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

5046 1.0

GF L013LP 130nm DDR DLL - 52MHz-260MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

5047 1.0

GF L013LP 130nm DDR DLL - 82MHz-410MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

5048 1.0

GF L013LP 130nm Deskew PLL - 180MHz-900MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

5049 1.0

GF L013LP 130nm Deskew PLL - 45MHz-225MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

5050 1.0

GF L013LP 130nm Deskew PLL - 90MHz-450MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...