651 10.0

Ethernet TSN Switch IP Core - Efficient and Massively Customizable Packet Architects offers a series of high speed switching/routing IP cores developed using the unique FlexSwitch tool-chain. This allows us to provide...

652 10.0

Multi Protocol Endpoint IP Core for Safe and Secure Ethernet Network "The CetraC EndSystem IP coreis the ideal solution to link your Avionic Computer System to a safe & secure embedded network as ARINC664p7, TSN or Safe...

653 10.0

Multi Protocol IO Concentrator (RDC) IP Core for Safe and Secure Ethernet Network Our IP Core is the ideal solution to link all your equipment, sensor or actuator whatever the used protocol to an Avionic network in a safe & secure m...

654 10.0

Automotive MIPI A-PHY Sink IP (2-Lane) The CL12912IP4000 is based on MIPI A-PHY interface specification announced in year 2020, targeting ultra-high-speed networking applications in ADAS an...

655 10.0

Automotive MIPI A-PHY Sink IP (2-Lane) The CL12912IP4000 is based on MIPI A-PHY interface specification announced in year 2020, targeting ultra-high-speed networking applications in ADAS an...

656 10.0

Automotive MIPI A-PHY Source IP - 1-Lane The CL12911IP4000 is based on MIPI A-PHY interface specification announced in year 2020, targeting ultra-high-speed networking applications in ADAS an...

657 10.0

Automotive MIPI A-PHY Source IP - 1-Lane The CL12911IP4000 is based on MIPI A-PHY interface specification announced in year 2020, targeting ultra-high-speed networking applications in ADAS an...

658 10.0

DVB-S2 Modulator IP Core DVBS2_TX.vhd is the transmitter top level component. Inputs consist of one or several streams (transport, generic). The output is a DDR complex baseba...

659 10.0

DVB-S2X Demodulator ASIC silicon proven IP Core ...

660 10.0

1x64 Bits OTP (One-Time Programmable) IP, Globa-Foundr--- 22nmFDX 0.8V/1.8V Process The AT1X64G22FDX0AA is organized as a 1 by 64 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in Globa-Foundr--- 22nm FD...

661 9.0

Camera High Dynamic Range IP - PINE The PINE with HDR functionality receives a fused Multi-exp. image from the sensor and processes it internally to extend the Dynamic Range of the image...

662 9.0

MIL-STD-1553 IP core MIL-STD-1553B IP Core implements MIL-STD?1553B standard and provides single or multi?functional interface between host processor and MIL-STD-1553 bus ...

663 9.0

ARINC664 End System IP Core ARINC664 End System IP is an IP Core that implements ARINC664 part 7 and provides interface between aircraft LRUs and ARINC664 network. As an implemen...

664 8.0

Camera 3DNR IP - AMUR (ME based) AMUR is a 3D Noise Reduction (3DNR) IP that effectively reduces noise in digital images. It is optimized for low light environment. AMUR uses Motion E...

665 8.0

Camera 3DNR IP - VINI (MA based) VINI is a 3D Noise Reduction (3DNR) IP that effectively reduces noise in digital images. It realizes high performance with low gate size and memory us...

666 8.0

MAXVY Universal Chiplet Interconnect Express (UCIe) Verification IP MAXVY UCIe VIP , a state-of-the-art solution that offers a comprehensive set of features and capabilities to ensure the quality and performance of you...

667 8.0

2D/3D OpenGL ES 2.0 vector graphics IP core - D/AVE NX D/AVE NX is the latest and most powerful addition to the D/AVE family of rendering cores. It is the first IP to bring 2D and 3D OpenGL ES 2.0 vector g...

668 8.0

MIPI I3C Verification IP The Maxvy's MIPI-I3C VIP provides configurable option to select I3C master/secondary master/slave based on the MIPI I3C DUT function as per user speci...

669 8.0

PRACH IP Suite Optimize your 5G NR O-RAN Split 7.2X design with EIC cutting-edge PRACH Design and Verification Suite. This comprehensive suite includes an end-to-end...

670 8.0

ARINC 429 IP Core ARINC 429 IP Core implements ARINC 429 standard. IP Core contains Rx and Tx processing blocks, Controller Block, Internal Memory and External Memory I...

671 8.0

ARINC 429 IP Core ARINC 429 IP Core implements ARINC 429 standard. IP Core contains Rx and Tx processing blocks, Controller Block, Internal Memory and External Memory I...

672 8.0

TSMC CLN7FF HBM2E PHY IP This datasheet describes GUC HBM (High Bandwidth Memory) PHY IP, which could be integrated with HBM memory controller to provide HBM functionality. Th...

673 8.0

Sub-GHz 433, 868, 915MHz IEEE 802.15.4 RF Transceiver IP The ShortLink Sub-GHz Transceiver RF IP 'SL40LP_Sub1GHzTrx_1' is a complete mixed signal RF IP for the 433, 868 and 915MHz frequency bands. It is comp...

674 7.5

LCD Panel Controller IP (Exclusively for Turnkey ASIC design; not for standalone licensing) This is an LCD Panel Controller IP that can drives multiple LCD panels available in the market. It is configurable to support 1/3-bias, 1/2 bias LCDs....

675 7.5

Temperature Sensor IP (Exclusively for Turnkey ASIC design; not for standalone licensing) This is a Temperature Sensor IP. It measures temperature variations within the IC and converts them in to digital form. The processor in the system ca...

676 7.5

Clock Management IP (Exclusively for Turnkey ASIC design; not for standalone licensing) This is a Clock Management IP that can drive 3 different output clocks. These 3 different clocks are required for any simple Digital or Mixed Signal A...

677 7.5

Power Management IP (Exclusively for Turnkey ASIC design; not for standalone licensing) This is a Power Management IP that can take 3 different input supplies and can drive 4 different output power domains. These 4 different power domains...

678 7.0

Falcon IP Core Falcon IP Core is a post-quantum digital signature algorithm (DSA). It is currently under development. It is going to be compliant with Falcon specifi...

679 7.0

Camera LDC (De-warp) IP - GINKGO GINKGO is an Lens Distortion Correction IP capable of up to 192° angle correction. It comes with factors that can adjust zoom and un-distortion streng...

680 7.0

Camera Scaler IP - DSCALE DSCALE is an IP that reduces the input image to a specified output size. DSCALE can simultaneously process one input image into four different reduce...

681 7.0

ECDSA IP Core ECDSA IP Cores perform digital signature generation and verification in compliance with the Elliptic Curve Digital Signature Algorithm (ECDSA) specifi...

682 7.0

AES GCM IP Core AES GCM IP Core is a Secure Symmetric Block Cipher IP Core that has compliance with the Advanced Encryption Standard (AES) specification in "FIPS 197"...

683 7.0

AES IP Core AES IP Core is a Secure Symmetric Block Cipher IP Core that has compliance with the Advanced Encryption Standard (AES) specification in "FIPS 197". Th...

684 7.0

SHA3 IP Core SHA3 IP Cores perform cryptographic hashing in compliance with the SHA-3 (Secure Hash Algorithm 3) specifications defined in 'FIPS 202'. This standard...

685 7.0

Dilithium IP Core Dilithium IP Core is a post-quantum digital signature algorithm (DSA). It currently supports Sign and Verify functions, with key generation functional...

686 7.0

Ultra Compact Ethernet TSN End Station Controller IP for Automotive The Ethernet TSN End Station Controller IP family from Comcores is a comprehensive hardware and software solution for automotive applications. The so...

687 7.0

DRBG IP Core DRBG IP Cores perform deterministic random bit generation in compliance with the standards and guidelines defined in 'NIST SP 800-90A'. This standard ...

688 7.0

TRNG IP Core TRNG IP Cores perform true random number generation in compliance with the standards and guidelines defined in 'NIST SP 800-90B'. This standard specif...

689 7.0

RSA IP Core RSA IP Cores perform digital signature generation and verification in compliance with the RSA (Rivest-Shamir-Adleman) Digital Signature Algorithm spec...

690 7.0

RSA Keygen IP Core RSA Keygen IP Cores perform key generation in compliance with the RSA Key Pair Generation specifications defined in 'FIPS 186'. This standard specifie...

691 7.0

DSC decoder IP DSC decoder IP is compliant with standard VESA Display Stream Compression version 1.1/1.2/1.2a....

692 7.0

KYBER IP Core Kyber IP is a core designed for Kyber post-quantum Key Encapsulation Mechanism (KEM). It currently supports the Encapsulation and Decapsulation functi...

693 6.0

Camera Demosaicing IP - DAISY (RCCC) The demosaicing is a color filter interpolation method, and refers to an image processing algorithm for restoring full color values of all pixels in a...

694 6.0

Camera Demosaicing IP - LOTUS (RCCB) The demosaicing is a color filter interpolation method, and refers to an image processing algorithm for restoring full color values of all pixels in a...

695 6.0

Camera Demosaicing IP - ROSE (RGB-IR) The demosaicing is a color filter interpolation method, and refers to an image processing algorithm for restoring full color values of all pixels in a...

696 6.0

Warping Engine IP block for image transformation, HUDs and fish-eye correction TES Warping Engine is a specialized IP core for arbitrary high-performance re-mapping of bitmaps from memory-to-memory or memory-to-stream. Applicatio...

697 6.0

Bluetooth BLE v5.3 PHY Silicon Proven Platinum IP icyTRX is a silicon-proven, ultra-low-power RF transceiver IP designed for Bluetooth Low Energy (BLE), IEEE 802.15.4 (e.g., ZigBee), and proprietary w...

698 6.0

Bluetooth Dual Mode PHY IP V5.4 Silicon Proven The icyTRX-DM is a Bluetooth® 5.4 Dual-Mode RF transceiver IP optimized for ultra-low power wireless communication. It supports both Bluetooth Classic...

699 6.0

DPI video output to system memory capture IP block The Virtual Display IP is designed to enable automated testing of the output of display controllers with DPI-2 output interface such as the TES CDC (C...

700 5.0

M31 ADC / Temp. Sensor IP in 12nm, 14nm, 22nm Process The M31 SAR ADC provides a rich portfolio with a resolution from 10 to 12-bit, maximum speed up to 2.5MSPS, and supports input types of single-ended o...