601 0.118

Input 400M-1600MHz, output 400M-1600MHz, all digital slave delay line of FXADDLL340HH0L to generate 25% delay in period of FREF, UMC 40nm LP/RVT Logic Process. Input 400M-1600MHz, output 400M-1600MHz, all digital slave delay line of FXADDLL340HH0L to generate 25% delay in period of FREF, UMC 40nm LP/RVT Logic...

602 0.118

Input 50M-210MHz, output 50M-210MHz. An all digital slave delay line of FXADDLL200HH0L to generate Programmable delay per 1/32 UI delay line UMC 40nm LP Logic Process Input 50M-210MHz, output 50M-210MHz. An all digital slave delay line of FXADDLL200HH0L to generate Programmable delay per 1/32 UI delay line UMC 40nm ...

603 0.118

Input 5M-300M Hz, output 20M-300M Hz, frequency synthesizable PLL; UMC 65nm Logic LL/RVT Low-k process Input 5M-300M Hz, output 20M-300M Hz, frequency synthesizable PLL; UMC 65nm Logic LL/RVT Low-k process...

604 0.118

Input 6M-27M Hz, output 10M-850M Hz, frequency synthesizable PLL; UMC 40nm Logic LP RVT and LVT process Input 6M-27M Hz, output 10M-850M Hz, frequency synthesizable PLL; UMC 40nm Logic LP RVT and LVT process...

605 0.118

Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 40nm Logic Process. Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in ...

606 0.118

Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPM Process Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 28nm Logic and Mi...

607 0.118

Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Process Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Proces...

608 0.118

Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Process Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Proces...

609 0.118

Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Process . Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Proces...

610 0.118

Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 50% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPM Process Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 50% delay in period of FREF,UMC 28nm Logic and Mix...

611 0.118

Input 80MHz-280MHz, DQS delay 3.125%-50% of FREF period, UMC 55nm SP/RVT Low-K logic process. Input 80MHz-280MHz, DQS delay 3.125%-50% of FREF period, UMC 55nm SP/RVT Low-K logic process....

612 0.118

Input 80MHz-280MHz, DQS delay 6.25%-50% of FREF period, UMC 40nm LP/RVT Low-K logic process. Input 80MHz-280MHz, DQS delay 6.25%-50% of FREF period, UMC 40nm LP/RVT Low-K logic process....

613 0.118

Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process. Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process....

614 0.118

Input VCC18V=1.8V, 1.8V Power On Reset for East-West Orientation; UMC 28nm HPC Logic Process Input VCC18V=1.8V, 1.8V Power On Reset for East-West Orientation; UMC 28nm HPC Logic Process...

615 0.118

Input VCC18V=1.8V, 1.8V Power On Reset for North-South Orientation; UMC 28nm HPC Logic Process Input VCC18V=1.8V, 1.8V Power On Reset for North-South Orientation; UMC 28nm HPC Logic Process...

616 0.118

Input VCC18V=1.8V, 1.8V Power On Reset; UMC 28nm HPC Logic Process Input VCC18V=1.8V, 1.8V Power On Reset; UMC 28nm HPC Logic Process...

617 0.118

Input VCC3V=3.3V, 3.3V Power On Reset without Vfr; UMC 55nm LP Logic Process Input VCC3V=3.3V, 3.3V Power On Reset without Vfr; UMC 55nm LP Logic Process...

618 0.118

Input VCC3V=3.3V, 3.3V Power On Reset; UMC 55nm LP Logic Process Input VCC3V=3.3V, 3.3V Power On Reset; UMC 55nm LP Logic Process...

619 0.118

Input VCC=0.9V, 0.9V Power On Reset without Vfr; UMC 28nm HPC Logic Process Input VCC=0.9V, 0.9V Power On Reset without Vfr; UMC 28nm HPC Logic Process...

620 0.118

Input VCC=1.1V& VCC3V=3.3V, 1.1/3.3V Power On Reset; UMC 40nm LP Logic Process Input VCC=1.1V& VCC3V=3.3V, 1.1/3.3V Power On Reset; UMC 40nm LP Logic Process...

621 0.118

Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm eflash Logic Process Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm eflash Logic Process...

622 0.118

Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm uLP Logic Process Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm uLP Logic Process...

623 0.118

Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm uLP/SST Logic Process Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm uLP/SST Logic Process...

624 0.118

Input VCC=1.2V& VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm LP Logic Process Input VCC=1.2V& VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm LP Logic Process...

625 0.118

Internal RC OSC, optional outout frequency 54MHz/27MHz/18MHz/13.5MHz, input VBG=0.8V; UMC 40nm LP/RVT Logic Process Internal RC OSC, optional outout frequency 54MHz/27MHz/18MHz/13.5MHz, input VBG=0.8V; UMC 40nm LP/RVT Logic Process...

626 0.118

Internal RC, output 40MHz with +/-5% frequency accuracy OSC, UMC 55nm SP/RVT Low-K logic Process Internal RC, output 40MHz with +/-5% frequency accuracy OSC, UMC 55nm SP/RVT Low-K logic Process...

627 0.118

Internal-R,output frequency 32 KHz, Input 0.99V-1.21V Oscillator. UMC 40nm LP/RVT Logic Process. Internal-R,output frequency 32 KHz, Input 0.99V-1.21V Oscillator. UMC 40nm LP/RVT Logic Process....

628 0.118

Internal-RC and Built-in Bandgap, trimmable fixed frequency 12MHz. Input 1.14V-1.26V; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process Internal-RC and Built-in Bandgap, trimmable fixed frequency 12MHz. Input 1.14V-1.26V; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...

629 0.118

Internal-RC, frequency 8MHz. Input 1.08V-1.32V ; UMC 55nm LP/RVT LowK Logic Process Internal-RC, frequency 8MHz. Input 1.08V-1.32V ; UMC 55nm LP/RVT LowK Logic Process...

630 0.118

Internal-RC, trimmable fixed frequency 1MHz. Input 1.14V-1.26V VBG=0.8V; UMC 0.11um EFLASH Logic Process Internal-RC, trimmable fixed frequency 1MHz. Input 1.14V-1.26V VBG=0.8V; UMC 0.11um EFLASH Logic Process...

631 0.118

Internal-RC, trimmable fixed frequency 80MHz. Power Supply: 3V-3.6V; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process Internal-RC, trimmable fixed frequency 80MHz. Power Supply: 3V-3.6V; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...

632 0.118

Voltage Detect Vdet1=2.8V,Vhys1=0.1V, Vdet2=2.6V, Vhys2=0.1V.Vdet2 rsie delay>10ms, fall delay<1ms. Generate high/low level logic for a precise power supply monitoring system; UMC 55nm eFlash Process Voltage Detect Vdet1=2.8V,Vhys1=0.1V, Vdet2=2.6V, Vhys2=0.1V.Vdet2 rsie delay>10ms, fall delay<1ms. Generate high/low level logic for a precise power ...

633 0.118

Voltage Detect Vdet=2.5V Vhys=0.1V, generate a high/low level logic for a precise power supply monitoring system; UMC 90nm SP/RVT LowK Logic Process Voltage Detect Vdet=2.5V Vhys=0.1V, generate a high/low level logic for a precise power supply monitoring system; UMC 90nm SP/RVT LowK Logic Process...

634 0.118

Voltage Detector IP, UMC 0.25um Logic process 0.25um process 2 level voltage detector, UMC 0.25um Logic process....

635 0.118

Voltage detector; UMC 55nm Logic SP/RVT Low-K Process Voltage detector; UMC 55nm Logic SP/RVT Low-K Process...

636 0.118

Voltage mode 10/100 Base-TX/FX Energy Efficient Ethernet PHY; Support EtherCAT and cable diagnostic; UMC 0.11um HS/AE Logic Process. Voltage mode 10/100 Base-TX/FX Energy Efficient Ethernet PHY; Support EtherCAT and cable diagnostic; UMC 0.11um HS/AE Logic Process....

637 0.118

ROM Compiler IP, UMC 0.162um Logic process UMC 0.162um Logic process synchronous diffusion programmable ROM memory compiler....

638 0.118

ROM Compiler IP, UMC 0.25um Logic process UMC 0.25um process synchronous VIA1 programmable ROM compiler....

639 0.118

Command/address block of 1:2 DDR2-PHY ; 0.11um HS/AE (AL Advanced Enhancement) Logic Process Command/address block of 1:2 DDR2-PHY ; 0.11um HS/AE (AL Advanced Enhancement) Logic Process...

640 0.118

Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process...

641 0.118

Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process...

642 0.118

Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process...

643 0.118

Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process...

644 0.118

Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process...

645 0.118

Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process...

646 0.118

Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process...

647 0.118

Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process...

648 0.118

Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version; UMC 40nm LP LVT/RVT LowK Logic Process Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version; UMC 40nm LP LVT/RVT...

649 0.118

compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process . compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process ....

650 0.118

Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process...