Design & Reuse
3739 IP
3551
0.0
WIFI6/BLE 5.2/BT 5.0 Combo RF IP (RFIP) in TSMC22
Provides a complete Dual Band WIFI6/BLE/BT Combo RF transceiver IP in 2.4G/5G, offering high-performance, low-power, and high reliability IP solutions...
3552
0.0
High Performance 64-Bit RISC-V Processor
StarFive Dubhe-90 is a high-performance commercial RISC-V CPU Core IP that is deliverable. It adopts an 11+ stage and 5-issue pipeline, superscalar, a...
3553
0.0
High performance-efficient deep learning accelerator for edge and end-point inference
AndesAIRE™ AnDLA™ I350 is a deep learning accelerator (DLA) designed to enable high performance-efficient and cost-sensitive AI solutions for edge and...
3554
0.0
High speed high performance 12-bit DAC
High performance DAC...
3555
0.0
High speed high performance 12-bit SAR ADC
Sequential Comparison Analog to Digital Converter (10 bits SAR-ADC)...
3556
0.0
Lightspeeur 2801S Neural accelerator
Lightspeeur® 2801 is the world's first commercially available deep learning CNN accelerator chip to run audio and video processing to power AI...
3557
0.0
Lightspeeur 2803S Neural accelerator
Lightspeeur® 2803 is the latest generation AI CNN accelerator for applications requiring high performance audio and video processing for advanced ...
3558
0.0
Lightspeeur 5801S Neural accelerator
The Lightspeeur 5801 is Gyrfalcon's 4th generation best-of-breed AI solution. It delivers the best AI performance of any neural accelerator on the...
3559
0.0
Signle Port High-Current SRAM Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option
Signle Port High-Current SRAM Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option...
3560
0.0
Signle Port High-Density SRAM Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option
Signle Port High-Density SRAM Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option...
3561
0.0
Signle Port Multi-Bank High-Density SRAM Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option
Signle Port Multi-Bank High-Density SRAM Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT...
3562
0.0
Silicon Security Solution
ChevinID™ was designed by Chevin Technology using patented method (GB2609026) to add a further layer of protection to your Silicon supply chain by ide...
3563
0.0
Silicon Storage Technology - Custom Design Services
Silicon Storage Technology, Inc. (SST), is the creator of SuperFlash® , an innovative, highly reliable and versatile type of NOR Flash memory. SST, th...
3564
0.0
Single Port SRAM Compiler IP, 4.0um2 bit cells, Synchronous high density, UMC 0.18um HV process
UMC 0.18um high voltage 1.8V process synchronous high density Single Port SRAM memory compiler....
3565
0.0
mioty - The Wireless IoT Technology
Wireless data transmission systems are being increasingly deployed in industrial and home automation applications. These robust systems are used to tr...
3566
0.0
MIPI C-PHY DSI RX IP
Innosilicon MIPI DSI RX IP implements the MIPI C-PHY as well as MIPI DSI protocols. The DSI link protocol specification is a part of group of communic...
3567
0.0
MIPI C-PHY DSI TX IP
Innosilicon MIPI DSI Transmitter implements the DSI protocol as well as MIPI C-PHY protocol. The DSI link protocol specification is a part of group of...
3568
0.0
MIPI C-PHY RX PHY
The Innosilicon MIPI C-PHY provides a C-PHY in a single IP core, which integrates a compatible PHY that supports high speed data receiver, plus a MIPI...
3569
0.0
MIPI C-PHY TX PHY
The Innosilicon MIPI C-PHY provides a C-PHY in a single IP core, which integrates a compatible PHY that supports high speed data receiver, plus a MIPI...
3570
0.0
MIPI C/D-PHY CSI-2 RX IP
Innosilicon CSI-2 Receiver implements MIPI CSI-2 as well as C/D-PHY protocols. The CSI-2 link protocol specification is a part of group of communicati...
3571
0.0
MIPI C/D-PHY RX
The Innosilicon MIPI C/D-PHY RX provides D-PHY and C-PHY in a single IP core. It integrates a compatible PHY that supports high speed data receiver, p...
3572
0.0
MIPI C/D-PHY TX
The Innosilicon MIPI C/D PHY TX integrates a MIPI C-PHY and a MIPI D-PHY in a single IP core, which provides a MIPI high speed data plus low-power low...
3573
0.0
MIPI CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
3574
0.0
MIPI CSI-2 TX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
3575
0.0
MIPI D-PHY Combo LVDS CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2, MIPI D-PHY, and LVDS protocols. The CSI-2 link protocol specification is a part of group of communication...
3576
0.0
MIPI D-PHY Combo LVDS DSI TX IP
Innosilicon MIPI DSI Transmitter implements DSI, MIPI D-PHY, and LVDS protocol. The DSI link protocol specification is a part of group of communicatio...
3577
0.0
MIPI D-PHY CSI-2 RX IP
Innosilicon CSI-2 Receiver implements MIPI CSI-2 protocol as well as D-PHY protocol. The CSI-2 link protocol specification is a part of group of commu...
3578
0.0
MIPI D-PHY DSI 1.2G RX IP
Innosilicon MIPI DSI receiver implements the MIPI DSI as well as D-PHY protocols. The DSI link protocol specification is a part of group of communicat...
3579
0.0
MIPI D-PHY DSI 1.5G RX IP
Innosilicon MIPI DSI RX IP implements the MIPI D-PHY as well as MIPI DSI protocols. The DSI link protocol specification is a part of group of communic...
3580
0.0
MIPI D-PHY DSI TX IP
Innosilicon MIPI DSI Transmitter implements the DSI protocol as well as MIPI D-PHY protocol. The DSI link protocol specification is a part of group of...
3581
0.0
MIPI D-PHY Receiver with PPI
SP_MIPI_DPHY_RX_PPI _T28HPCP is a MIPI D-PHY Receiver, which complies with MIPI D-PHY specification version 1.2. This D-PHY design receives data from ...
3582
0.0
MIPI D-PHY RX/TX v1.1 / v1.2 IP in TSMC (12/16nm, 28nm, 40nm, and 55nm process)
The D-PHY is a popular MIPI physical layer developed for mobile applications because it is a flexible, high-speed, low-power and low-cost solution. As...
3583
0.0
MIPI D-PHY TX
The Innosilicon MIPI D-PHY TX provides a MIPI® high speed data plus low-power low speed transmitter that supports data transfer in the bi-directional ...
3584
0.0
MIPI D-PHY TX COMBO LVDS PHY
The Innosilicon MIPI D-PHY TX combo LVDS PHY integrates a D-PHY and a LVDS in a single IP core, which provides a MIPI® high speed data plus low-power ...
3585
0.0
MIPI D-PHY TX Combo TTL PHY
The Innosilicon MIPI D-PHY TX provides a MIPI® high speed data plus low-power low speed transmitter that supports data transfer in the bi-directional ...
3586
0.0
MIPI D-PHY_1.2G CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
3587
0.0
MIPI D-PHY_1.5G CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
3588
0.0
MIPI D-PHY_2.5G CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
3589
0.0
MIPI D-PHY_4.5G CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
3590
0.0
MIPI DPHY DSI TX IP
Innosilicon MIPI DSI Transmitter implements the DSI protocol as well as MIPI D-PHY protocol. The DSI link protocol specification is a part of group of...
3591
0.0
MIPI DPHY1.2 RX (support combo TTL, LVDS, HiSPI)
The Innosilicon MIPI D-PHY IP provides D-PHY in a single IP core. It integrates a compatible PHY that supports high speed data receiver, plus a MIPI® ...
3592
0.0
MIPI DPHY2.0/CPHY1.1 TX (support combo TTL, LVDS, HiSPI)
The Innosilicon MIPI C/D PHY TX integrates a MIPI C-PHY and a MIPI D-PHY in a single IP core, which provides a MIPI high speed data plus low-power low...
3593
0.0
MIPI DSI-2 DSC RX IP
Innosilicon MIPI DSI-2 DSC RX IP implements the MIPI C/D-PHY as well as MIPI DSI-2 protocols and contains the DSC (Display Stream Compression) algorit...
3594
0.0
MIPI M-PHY
INNOSILICON™ M-PHY IP implements the MIPI M-PHY protocol V4.1. The M-PHY protocol specification is a part of a group of communication protocols define...
3595
0.0
Circuit Camouflage Technology
Rambus Circuit Camouflage Technology (formerly Inside Secure), also known as SecureMedia Library (SML), is an anti-reverse engineering and anti-clonin...
3596
0.0
VIS 150nm 5V Bandgap voltage reference
The OT0118 is a medium precision, bandgap voltage reference and current reference generator specifically tuned for the VIS 150nm CMOS process....
3597
0.0
8Kx16 Bits OTP (One-Time Programmable) IP, D- HiTe- AN180 1.8V / 5V Process
The ATO008KX16DB180AO15NA is organized as 8Kx16 One-Time Programmable in 16-bit read and 1-bit program modes. This is a kind of non-volatile memory su...
3598
0.0
8Kx16 Bits OTP (One-Time Programmable) IP, VI- 110nm E-Flash 1.5V/3.3V Process
The ATO008KX16VI110EFM5DA I-fuse® IP is organized as 8Kx16 bits one-time programmable (OTP). This is a kind of non-volatile memory fabricated in VI- 1...
3599
0.0
1Kx32 Bits OTP (One-Time Programmable) IP, TSM- 40ULP 1.1/2.5V Process
The AT1K32T40ULP6AA is organized as a 1K-bit by 32 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in TSM- 40ULP 1.1/2.5...
3600
0.0
8Kx8 Bits OTP (One-Time Programmable) IP, MXI- 0.18μm 1.8V/5V Logic/BCD Process
The ATO0008KX8MX180LBX4DC is organized as a 8k x 8 one-time programmable in parallel mode. This is a kind of non-volatile memory fabricated in MXIC 0....