Innosilicon Technology Ltd IP Cores

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1551

0.118

DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.162um LL process

Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.162um Logic process....

1552

0.118

DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz -200MHz, UMC 0.18um G2 process

Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.18um GII Logic process....

1553

0.118

DDR DLL IP, Input: 100MHz - 400MHz, Output: 100MHz - 400MHz, UMC 65nm SP process

Input 100-400MHz, output 100-400MHz, DDR2 DLL, UMC 65nm SP/RVT Low-K Logic process....

1554

0.118

DDR DLL IP, Input: 192MHz - 400MHz, Output: 96MHz - 200MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process

UMC 0.13um HS/FSG process DLL-based cell that generates fouRchannel DQS with 13.5% ~ 36.6% timing delay for DDR1 SDRAM controller usage....

1555

0.118

DDR DLL IP, Input: 200MHz - 333MHz, Output: 200MHz - 333MHz, UMC 90nm SP process

Input 200-333MHz, output 200-333MHz, DDR2 DLL, UMC 90nm SP/RVT Low-K Logic process....

1556

0.118

DDR DLL IP, Input: 200MHz - 400MHz, Output: 200MHz - 400MHz, UMC 55nm SP process

Input 200-400MHz, output 200-400MHz, DDR2 DLL, UMC 55nm SP Low-K Logic process....

1557

0.118

DDR DLL IP, Input: 333MHz - 667MHz, Output: 333MHz - 667MHz, UMC 90nm SP process

Input 333M-667MHz, output 333M-667MHz, DDR2/3 Multi-phase DLL, UMC 90nm SP/RVT Low-K Logic process....

1558

0.118

DDR DLL IP, Input: 400MHz - 533MHz, Output: 200MHz - 266MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process

It is a UMC 0.13um HS DLL-based cell that generates three-channel DQS with 13.5% ~ 36.6% timing delay for DDR2 SDRAM controller usage....

1559

0.118

DDR DLL IP, Input: 66MHz - 133MHz, Output: 66MHz - 133MHz, UMC 0.13um HS/FSG process

Input 66M-133MHz, output 66M-133MHz, DDR DLL, UMC 0.13um HS/FSG Logic process....

1560

0.118

DDR DLL IP, Input: 66MHz - 200MHz, Output: 66MHz - 200MHz, UMC 90nm SP process

Input 66M-200MHz, output 66M-200MHz, DDR DLL, UMC 90nm SP/RVT Low-K Logic process....

1561

0.118

DDR DLL IP, Input: 80MHz - 320MHz, Output: 6.25%-50% Delay, UMC 55nm SP process

Input 80-320MHz, output 6.25%~50% delay, 80-320MHz, DDR2 DLL, UMC 55nm SP/RVT Low-K Logic process....

1562

0.118

DDR1/MDDR PHY CMD/ADDR BLOCK ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process

DDR1/MDDR PHY CMD/ADDR BLOCK ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process...

1563

0.118

DDR1/MDDR PHY Data block ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process

DDR1/MDDR PHY Data block ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process...

1564

0.118

DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process

DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process...

1565

0.118

DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process

DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process...

1566

0.118

DDR2 PHY compensation block for 171 series (non BOAC); UMC 0.13um HS/FSG Logic Process

DDR2 PHY compensation block for 171 series (non BOAC); UMC 0.13um HS/FSG Logic Process...

1567

0.118

DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process

DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process...

1568

0.118

DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process

DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process...

1569

0.118

DDR2 PHY Data Block ;UMC 0.13um Logic HS/FSG Process

DDR2 PHY Data Block ;UMC 0.13um Logic HS/FSG Process...

1570

0.118

DDR2-PHY command/address block for DRAM chip, BOAC ; UMC 90nm SP/RVT Low-K Logic Process

DDR2-PHY command/address block for DRAM chip, BOAC ; UMC 90nm SP/RVT Low-K Logic Process...

1571

0.118

DDR2-PHY Command/Address block; UMC 90nm SP/RVT Lowk Process

DDR2-PHY Command/Address block; UMC 90nm SP/RVT Lowk Process...

1572

0.118

DDR2-PHY compensation block, BOAC; UMC 0.13um HS/FSG process

DDR2-PHY compensation block, BOAC; UMC 0.13um HS/FSG process...

1573

0.118

DDR2-PHY compensation block, BOAC; UMC 90nm SP/RVT Low-K Logic process

DDR2-PHY compensation block, BOAC; UMC 90nm SP/RVT Low-K Logic process...

1574

0.118

DDR2-PHY data block with BOAC IO; UMC 90nm SP/RVT Lowk Logic Process

DDR2-PHY data block with BOAC IO; UMC 90nm SP/RVT Lowk Logic Process...

1575

0.118

DDR2-PHY data block; UMC 90nm SP/RVT Lowk Process

DDR2-PHY data block; UMC 90nm SP/RVT Lowk Process...

1576

0.118

DDR2/3 Combo Command /Address Block (with 2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Process

DDR2/3 Combo Command /Address Block (with 2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Process...

1577

0.118

DDR2/3 COMBO Compensation block (2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Porcess

DDR2/3 COMBO Compensation block (2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Porcess...

1578

0.118

DDR2/3 Controller IP, DDR2/3 controller with DFI 2.1 interfaces, Support DDR1/DDR2/DDR3 SDRAM, Soft IP

DDR2/3 Combo SDRAM Controller....

1579

0.118

DDR2/3 PHY Combo PHY data block (1.0v SP & 2.5V device); UMC 90nm SP/RVT LowK Logic Process

DDR2/3 PHY Combo PHY data block (1.0v SP & 2.5V device); UMC 90nm SP/RVT LowK Logic Process...

1580

0.118

DDR2/DDR1/MDDR Combo Command/Address Block ; UMC 65nm LP/RVT LowK Logic Process

DDR2/DDR1/MDDR Combo Command/Address Block ; UMC 65nm LP/RVT LowK Logic Process...

1581

0.118

DDR2/DDR1/MDDR Combo Data Block ; UMC 65nm LP/RVT LowK Logic Process

DDR2/DDR1/MDDR Combo Data Block ; UMC 65nm LP/RVT LowK Logic Process...

1582

0.118

DDR2/MDDR Combo Command/Address Block ; UMC 0.13um HS/FSG Logic Process

DDR2/MDDR Combo Command/Address Block ; UMC 0.13um HS/FSG Logic Process...

1583

0.118

DDR2/MDDR Combo Data Block ; 0.13um Logic HS/FSG Logic Process

DDR2/MDDR Combo Data Block ; 0.13um Logic HS/FSG Logic Process...

1584

0.118

DDR2/MDDR Combo PHY CMD ADDR block ; UMC 55nm SP/RVT Lowk Process with 2.5V device

DDR2/MDDR Combo PHY CMD ADDR block ; UMC 55nm SP/RVT Lowk Process with 2.5V device...

1585

0.118

DDR2/MDDR Combo PHY data block ; UMC 55nm SP process with 2.5V device

DDR2/MDDR Combo PHY data block ; UMC 55nm SP process with 2.5V device...

1586

0.118

DDR2/MDDR COMBO PHY Data block for Chip usage ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process

DDR2/MDDR COMBO PHY Data block for Chip usage ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process...

1587

0.118

DDR2/MDDR Combo PHY for Chip load usage ; UMC 65NM SP-RVT with 2.5V device LowK Logic Process

DDR2/MDDR Combo PHY for Chip load usage ; UMC 65NM SP-RVT with 2.5V device LowK Logic Process...

1588

0.118

DDR2/MDDR PHY CMD/ADDR BLOCK ; UMC 65nm 1.0V process with 2.5V device SP/RVT Lowk Logic Process

DDR2/MDDR PHY CMD/ADDR BLOCK ; UMC 65nm 1.0V process with 2.5V device SP/RVT Lowk Logic Process...

1589

0.118

DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage ; UMC 65nm 1.0V with 2.5V Device SP/RVT LowK Logic Process

DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage ; UMC 65nm 1.0V with 2.5V Device SP/RVT LowK Logic Process...

1590

0.118

DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage; UMC 55nm 1.0V with 2.5V device SP/RVT LowK Logic Process

DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage; UMC 55nm 1.0V with 2.5V device SP/RVT LowK Logic Process...

1591

0.118

DDR2/MDDR PHY Data block ; UMC 65nm 1.0V with 2.5V device SP/RVT LowK Logic Process

DDR2/MDDR PHY Data block ; UMC 65nm 1.0V with 2.5V device SP/RVT LowK Logic Process...

1592

0.118

DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device

DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device...

1593

0.118

DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device for 2 layer PCB board usage

DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device for 2 layer PCB board usage...

1594

0.118

DDR23 COMBO PHY compensation Block ; UMC 40LP/RVT LowK Logic Process with 2.5V device

DDR23 COMBO PHY compensation Block ; UMC 40LP/RVT LowK Logic Process with 2.5V device...

1595

0.118

DDR23 COMBO PHY Data Block ; UMC 40nm LP/RVT LowK Logic Process with 2.5V device

DDR23 COMBO PHY Data Block ; UMC 40nm LP/RVT LowK Logic Process with 2.5V device...

1596

0.118

DDR23 COMBO PHY Data Block ; UMC 40nm LP/RVT LowK Logic Process with 2.5V device (16Bit)

DDR23 COMBO PHY Data Block ; UMC 40nm LP/RVT LowK Logic Process with 2.5V device (16Bit)...

1597

0.118

DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process

DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process...

1598

0.118

DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process

DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process...

1599

0.118

DDR3 Combo PHY Compensation Block for solder bump application; UMC 40nm LP/RVT Logic Process

DDR3 Combo PHY Compensation Block for solder bump application; UMC 40nm LP/RVT Logic Process...

1600

0.118

DDR3 Combo PHY Data Block for solder bump application; UMC 40nm LP/RVT Logic Process

DDR3 Combo PHY Data Block for solder bump application; UMC 40nm LP/RVT Logic Process...

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