Design & Reuse
915 IP
551
1.0
95 dB of SNR, 24-bit stereo audio CODEC with AGC and headphone output in TSMC 65LP
SoC integrators wishing to address portable audio applications like Smart Phones, PMP or Portable Multimedia Devices for mobile communication, should ...
552
1.0
Nano power DC-DC converter with ultra-low quiescent current and high efficiency at light load in TSMC 22ULL
DCDC-ULP-T22-1.62-3.63-0.6-2.5.01_TSMC_22_ULL is a Nano power DC-DC converter in TSMC 22ULL with ultra-low quiescent current and high efficiency at li...
553
1.0
LDO regulator in SMIC 40nm, 0.6~1.1v output
The present IP is a low dropout voltage regulator, which can support 10uA current load. The input voltage is 2.7-3.6V (typical: 3.3V). Its output volt...
554
1.0
LDO regulator in SMIC 40nm, 1.13v output
The present IP is a low dropout voltage regulator, which can support 10uA DC current load. The input voltage is 2.7-3.6V (typical: 3.3V). Its output v...
555
1.0
LDO regulator in SMIC 40nm, 1.42v output
The present IP is a low dropout voltage regulator, which can support 10uA DC current load. The input voltage is 2.7-3.6V (typical: 3.3V). Its output v...
556
1.0
LDO regulator in SMIC 40nm, 2.1v output
The present IP is a low dropout voltage regulator, which can support 360uA current load. The input voltage is 2.7-3.6V (typical: 3.3V). Its output vol...
557
1.0
LDO regulator in SMIC 40nm, up to 12mA
The present IP is a low-dropout (LDO) voltage regulator supporting a 12mA load current with an input voltage range of 2.7V to 3.6V (typical: 3.3V). It...
558
1.0
LDO regulator in SMIC 65nm, capless
The present IP is a low-dropout (LDO) and capacitor-less voltage regulator developed using SMIC's 65nm ETOX Nor Flash process. It generates adjustable...
559
1.0
eDP v1.5a RX PHY (14nm)
The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1Gbps), and the general mode supports a maximum data rate of up to 4Gbps. This core IP is...
560
1.0
eDP v1.5a RX PHY (14nm)
The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1Gbps), and the general mode supports a maximum data rate of up to 4Gbps. This core IP is...
561
1.0
eDP v1.5a RXPHY (14nm)
The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1 Gbps), and the general mode supports a maximum data rate of up to 4 Gbps. This core IP ...
562
1.0
Temperature Sensor with PTAT voltage output
The present IP is Temperature sensor (TS) circuit. Which generates the PTAT voltage into an external ADC block for the sensing of temperature....
563
1.0
Retention Alternative Regulator, combines a linear regulator and an ultra-low quiescent regulator for sleep mode in TSMC 55uLP
RAR-iLR-qLR-1.62-3.63-0.55-2.5.01_TSMC_55_uLP is a Retention Alternating Regulator in TSMC 55uLP combining two regulation sub-components: a linear reg...
564
1.0
Charge-Pump negative voltage generator with adjustable wide range on SMIC65nm
The present IP is a charge-pump voltage generator developed using SMIC's 65nm ETOX Nor Flash process. It generates high voltages ranging from -10.1V t...
565
1.0
Charge-Pump positive voltage generator with adjustable wide range on SMIC65nm
The present IP is a charge-pump voltage generator developed using SMIC's 65nm ETOX Nor Flash process. It generates high voltages ranging from 3.6V to ...
566
1.0
Charge-Pump positive voltage generator with LDO in-built on SMIC65nm
The present IP is a charge-pump and low dropout voltage generator, which is developed with SMIC 65nm ETOX Nor Flash process. And it generates 4.5~6v h...
567
1.0
WhisperExtractor, 7 µW always on Audio feature extraction
WhisperExtractor is a disruptive technology in TSMC 22ULL that addresses a major challenge in the voice user interaction space - low power consumption...
568
1.0
Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks in TSMC 55uLP
nLR-Charny-ref-1.62-3.63-0.8-2.5.03_TSMC_55_uLP is a Low-noise LDO in TSMC 55uLP, tailored for RF....
569
1.0
Linear regulator, low-noise optimized for sensitive analog loads such as CODEC and Reference in SMIC 55LL
nLR-VAIPO-2.90-3.63-2.5.01_SMIC_55_LL is a low-noise linear regulator LDO in SMIC 55LL for sensitive analog blocks....
570
1.0
Linear regulator, low-noise optimized for sensitive analog loads such as CODEC and Reference in TSMC 55LP
nLR-VAIPO-2.90-3.63-2.5.01_TSMC_55_LP is a low-noise linear regulator LDO in SMIC 55LP for sensitive analog blocks....
571
1.0
Linear Regulator, ultra low quiescent current for retention mode in TSMC 40LP
qLR-Aubrey-ref-1.62-3.63-0.55-2.5.02_TSMC_40_LP is an ultra-low quiescent LDO (Linear regulator) in TSMC 40LP....
572
1.0
MIPI D-PHY TRx 2.15Gbps (28nm)
The MIPI D-PHY IP supports data rates of up to 2.15Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provi...
573
1.0
MIPI D-PHY TRx 2.1Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.1Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
574
1.0
SLVS-EC 2.0 RX PHY (14nm)
The SLVS-EC Receiver PHY IP consists of a hard macro architecture compliant with SLVS-EC version 2.0 specification, supporting data rate up to 10 Gbps...
575
1.0
SLVS-EC 3.0 RX PHY (4nm)
The SLVS-EC Receiver PHY IP consists of a hard macro architecture compliant with SLVS-EC version 3.0 specification, supporting data rate up to 10 Gbps...
576
1.0
Always-on Voice Activity Detection interfacing with analog microphones in GF 55LPx
WT-a-HD.03_GF_55_LPx is a mixed analog/digital Virtual Component (ViC) in GF 55LPx containing a Voice Activity Detection (VAD) engine for ultra low po...
577
1.0
Always-on Voice Activity Detection interfacing with analog microphones in SMIC 40LL
WT-a-HD.01_SMIC_40_LL is a mixed analog/digital Virtual Component (ViC) in SMIC 40LL containing a Voice Activity Detection (VAD) engine for ultra low ...
578
1.0
Always-on Voice Activity Detection interfacing with analog microphones in SMIC 40uLP
WT-a-HD.03_SMIC_40_uLP is a mixed analog/digital Virtual Component (ViC) in SMIC 40uLP containing a Voice Activity Detection (VAD) engine for ultra lo...
579
1.0
Always-on Voice Activity Detection interfacing with analog microphones in TSMC 22ULL
WT-a-HD.03_TSMC_22_uLL is a mixed analog/digital Virtual Component (ViC) in TSMC 22ULL containing a Voice Activity Detection (VAD) engine for ultra-lo...
580
1.0
Always-on Voice Activity Detection interfacing with analog microphones in TSMC 40uLP
WT-a-HD.03_TSMC_40_uLP is a mixed analog/digital Virtual Component (ViC) in TSMC 40uLP containing a Voice Activity Detection (VAD) engine for ultra lo...
581
1.0
Always-on Voice Activity Detection interfacing with analog microphones in TSMC 40uLP
WT-a-HD.01_TSMC_40_uLP is a mixed analog/digital Virtual Component (ViC) in TSMC 40uLP containing a Voice Activity Detection (VAD) engine for ultra lo...
582
1.0
Always-on Voice Activity Detection interfacing with analog microphones in TSMC 55uLP
WT-a-HD.03_TSMC_55_uLP is a mixed analog/digital Virtual Component (ViC) in TSMC 55uLP containing a Voice Activity Detection (VAD) engine for ultra lo...
583
1.0
Intra-Panel Multi Strandard Low-Power TX PHY (28nm)
The Intra-Panel TX PHY is a COG and COF transmitter supporting up to 3.2Gbps data rate with low power consumption. It features a DC-coupled differenti...
584
1.0
Intra-Panel Multi Strandard TX PHY (14nm)
The Intra-Panel TX PHY is a COG and COF transmitter supporting up to 3.6Gbps data rate with low power consumption. It features a DC-coupled differenti...
585
1.0
Intra-Panel Multi Strandard TX PHY (8nm)
The Intra-Panel TX PHY is a COG and COF transmitter supporting up to 4.0Gbps data rate with low power consumption. It features a DC-coupled differenti...
586
1.0
voltage buffer in SMIC 65nm
The present IP is a voltage reference buffer, which is developed with SMIC 65nm ETOX Nor Flash process. And It generates a reference voltage with load...
587
1.0
Combined Power On Reset and Brown Out Reset - High temperature (Grade 1, Tj=150°) in TSMC 40uLPeF
POR-BOR-LS-1.62-3.63-0.55-3.3.02_TSMC_40_uLPeF is a combined Power On Reset and Brown Out Reset in TSMC 40uLPeF. Designed for extended mission profile...
588
1.0
Comparator with configurable hysteresis input
This present IP is a comparator which is used to do the comparison between the different input groups, which operates in 3.3v power supply, the output...
589
1.0
Comparator with low-quiescent Hysteresis in TSMC 180eLL
qCMPH-LP-RR-2.0-3.63-1.2-1.98.02_TSMC_180_eLL is a comparator with low-quiescent hysteresis, designed to extract data from the RF waveform in normal m...
590
1.0
Comparator with low-quiescent Hysteresis in TSMC 180eLL
qCMPH-RR-2.0-3.63-1.2-1.98.02_TSMC_180_eLL is a comparator in TSMC 180eLL with low-quiescent hysteresis is designed to extract data from the RF wavefo...
591
1.0
Comparator with low-quiescent Hysteresis in TSMC 55uLPeF
qCMPH-LP-RR-1.62-3.63.01_TSMC_55_uLPeF is a comparator in TSMC 55uLPeF with low-quiescent hysteresis, designed to extract data from the RF waveform in...
592
1.0
Low Power BandGap Reference in SMIC 40nm
The BGR IP is a BangGap Reference for low-power application. The output reference voltage are two fixed voltage:0.6v/1.2v and two adjustable voltage r...
593
1.0
Low Power BandGap Reference in SMIC 65nm
The BGR IP is a BandGap reference circuit for low-power application which just consumes 3.2uA in operation which works well in 1.55~4v power supply. T...
594
1.0
Low Power BandGap Reference with chopper in SMIC 40nm
The IP is a Band-gap reference generator circuit. In the core block, with the use of chopper, the random error caused by the offset of the opamp is co...
595
1.0
Low-Power Over-voltage Protection Module to handle Over-voltage operation (up to 3.63 V) while using standard process 1.8 V devices in GF 22FDX
OPM-Angel-AR-LP-1.62-3.63-1.8.02_GF_22_FDX is an Over-voltage Protection Module companion for regulators in GF 22FDX enabling over-voltage operations ...
596
1.0
DP 1.4 / eDP v1.4b TXPHY (14nm)
The eDP v1.4b TX PHY IP consists of a hard macro architecture supporting embedded DisplayPort v1.4 specification with data rates up to 8.1 Gbps per la...
597
1.0
DP 1.4 / eDP v1.4b TXPHY (4nm)
The eDP v1.4b TX PHY IP consists of a hard macro architecture supporting embedded DisplayPort v1.4 specification with data rates up to 8.1 Gbps per la...
598
1.0
DP 1.4 / eDP v1.4b TXPHY (8nm)
The eDP v1.4b TX PHY IP consists of a hard macro architecture supporting embedded DisplayPort v1.4 specification with data rates up to 8.1 Gbps per la...
599
1.0
DP 2.1a / eDP v1.5a RXPHY (4nm)
The DP/eDP RX PHY supports a maximum data rate of up to HBR3 (8.1 Gbps), and the general mode supports a maximum data rate of up to 4 Gbps. This core ...
600
1.0
Up to 105 dB of SNR, 24-bit mono CODEC with PDM to PWM transmodulator DAC and embedded regulator in TSMC 55LP
sCODa-MT1-LR01_TSMC_55_LP is an audio CODEC in TSMC 55LP which provides the insurance of the best sound quality after integration into a SoC for low p...