Design & Reuse
Catalog of SIP Cores
System on Chip design resources
941 IP
701
0.0
DDR combo IO in SMIC 28HKD 0.9/1.8V, supporting DDR3,4/LPDDR3,4, upto 2667Mbps
Brite DDR (Double Data Rate SDRAM) IO libraries cover wide range of DDR standards, from DDR2 to DDR4 and LPDDR2 to LPDDR4X with the data rate from 200...
702
0.0
DDR combo IO in SMIC 28HKD 0.9/2.5V, supporting DDR2,3/LPDDR2,3, upto 1600Mbps for IOT application
Brite DDR (Double Data Rate SDRAM) IO libraries cover wide range of DDR standards, from DDR2 to DDR4 and LPDDR2 to LPDDR4X with the data rate from 200...
703
0.0
DDR combo IO in SMIC 28HKD 0.9/2.5V, supporting DDR3,4/LPDDR3,4, upto 1866Mbps
Brite DDR (Double Data Rate SDRAM) IO libraries cover wide range of DDR standards, from DDR2 to DDR4 and LPDDR2 to LPDDR4X with the data rate from 200...
704
0.0
DDR combo IO in SMIC 40NLL, supporting DDR2,3/LPDDR2,3, upto 1333Mbps
Brite DDR (Double Data Rate SDRAM) IO libraries cover wide range of DDR standards, from DDR2 to DDR4 and LPDDR2 to LPDDR4X with the data rate from 200...
705
0.0
DDR combo IO in SMIC 40NLL, supporting DDR3,3U,3L,4/LPDDR2,3, upto 1866Mbps
Brite DDR (Double Data Rate SDRAM) IO libraries cover wide range of DDR standards, from DDR2 to DDR4 and LPDDR2 to LPDDR4X with the data rate from 200...
706
0.0
DDR combo IO in SMIC 55NLL, supporting DDR2/3/3L /LPDDR2/3, upto 1333Mbps
Brite DDR IO libraries cover wide range of DDR standards, from DDR2 to DDR4 and LPDDR2 to LPDDR4X with the data rate from 200Mbps to 4805Mbps. Brite p...
707
0.0
DDR123/LPDDR23 in SMIC 55NLL
Brite Semiconductor provides a complete DDR subsystem including not only controller, PHY and IO, also corresponding tuning and configuration software....
708
0.0
DDR2,3/LPDDR2,3 combo DDR PHY+ Controller upto 1333Mbps in SMIC 55NLL
Brite Semiconductor provides a complete DDR subsystem including not only controller, PHY and IO, also corresponding tuning and configuration software....
709
0.0
DDR23/LPDDR23 in SMIC 40NLL
Brite Semiconductor provides a complete DDR subsystem including not only controller, PHY and IO, also corresponding tuning and configuration software....
710
0.0
DDR23/LPDDR23 PHY+Controller in SMIC 28HKD 0.9/2.5V
DDR23/LPDDR23 combo DDR PHY + Controller upto 1600Mbps for IoT application...
711
0.0
DDR34/LPDDR23 in SMIC 40NLL
Brite Semiconductor provides a complete DDR subsystem including not only controller, PHY and IO, also corresponding tuning and configuration software....
712
0.0
DDR34/LPDDR34 PHY in SMIC 28HKC+
Brite Semiconductor provides a complete DDR subsystem including not only controller, PHY and IO, also corresponding tuning and configuration software....
713
0.0
DDR34/LPDDR34 PHY in SMIC 28HKD 0.9/1.8V
Brite Semiconductor provides a complete DDR subsystem including not only controller, PHY and IO, also corresponding tuning and configuration software....
714
0.0
DDR34/LPDDR34 PHY in SMIC 28HKD 0.9/2.5V
Brite Semiconductor provides a complete DDR subsystem including not only controller, PHY and IO, also corresponding tuning and configuration software....
715
0.0
DDR4 & LPDDR4 COMBO IO for memory controller PHY, 3200Mbps, TSMCN22
The DDR4&LPDDR4 COMBO IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM device. The TX is designe...
716
0.0
DDR4 in SMIC 55NLL
Brite Semiconductor provides a complete DDR subsystem including not only controller, PHY and IO, also corresponding tuning and configuration software....
717
0.0
DDR4IO for memory PHY, 3200Mbps
The DDR4 IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM device. The TX is designed to send inf...
718
0.0
DDR5 PHY&MAC - high performance and low power
With sophisticated architecture and advanced technology, KNiulink provide DDR5 with high performance and low power. In advanced process nodes, KNiuli...
719
0.0
DDR5 & DDR4 COMBO IO for memory controller PHY, 4800Mbps, TSMCN12
The DDR5&DDR4 COMBO IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM device. The TX is designed ...
720
0.0
VectorPath Accelerator Card
The VectorPath™ S7t-VG6 accelerator card is designed to reduce time to market when developing high-performance compute and acceleration function...
721
0.0
Register File with low power retention mode and 3 speed options
Low Leakage. Mobile Semiconductor's RF1P-ULL-GF22FDX-PLUS memory compiler generates single-port Register File instances using the GLOBALFOUNDRIES 22nm...
722
0.0
Register File with low power retention mode and 3 speed options
Low Leakage. Mobile Semiconductor's SP-ULD-GF22FDX-PLUS memory compiler generates single-port Register File instances using the GLOBALFOUNDRIES 22nm F...
723
0.0
Register File with low power retention mode, high speed pins on 1 side
Low Leakage. Mobile Semiconductor's Bulk 22 ULL Register file memory compiler generates single-port Register File instances using the Bulk 22ULL proce...
724
0.0
Temperature Sensor with 10Bit Digital output
The present IP is a high accuracy and highly integrated temperature sensor. It consists of analog front-end (TS_FE) and back-end (SDADC). TS_FE is to ...
725
0.0
Temperature Sensor with PTAT voltage output
The present IP is Temperature sensor (TS) circuit. Which generates the PTAT voltage into an external ADC block for the sensing of temperature....
726
0.0
Geon Secure Execution Processor
Geon Secure Execution Processor delivers secure code execution by supporting two secure contexts. All code and data belonging to a secure context is c...
727
0.0
JESD204B RX IP
With sophisticated architecture and advanced technology, JESD204B RX IP with PHY only is designed for low power and high-performance application. It i...
728
0.0
JESD204B TX IP
With sophisticated architecture and advanced technology, JESD204B PMA IP is designed for low power and high performance application. It is fully compa...
729
0.0
Metal programmable ROM compiler - Memory optimized for low power - compiler range up to 1024 k
Foundry Sponsored - Metal programmable ROM compiler - TSMC 90 nm LPeF - Non volatile memory optimized for low power - compiler range up to 1024 k...
730
0.0
Metal programmable ROM compiler - Memory optimized for low power - compiler range up to 256 k
Metal programmable ROM compiler - TSMC 65 nm LP - Non volatile memory optimized for low power - compiler range up to 256 k...
731
0.0
Metal programmable ROM compiler - Memory optimized for low power - compiler range up to 256 k
Foundry Sponsored - Metal programmable ROM compiler - TSMC 130 nm BCD - Non volatile memory optimized for low power - compiler range up to 256 k...
732
0.0
Metal programmable ROM compiler - Memory optimized for low power - Dual Voltage - compiler range up to 1024 k
Metal programmable ROM compiler - TSMC 130 nm G - Non volatile memory optimized for low power - Dual Voltage - compiler range up to 1024 k...
733
0.0
Metal programmable ROM compiler - Non volitile memory optimized for low power - compiler range up to 256 k
Metal programmable ROM compiler - TSMC 130 nm BCD Plus - Non volatile memory optimized for low power - compiler range up to 256 k...
734
0.0
Retention Alternative Regulator combining a linear regulator and an ultra-low quiescent regulator for sleep mode in TSMC 40uLPeF
RAR-iLR-qLR-ref-1.62-3.63-0.55-2.5.01_TSMC_40_uLPeF is a Retention Alternating Regulator in TSMC 40uLPeF combining two regulation sub-components: a li...
735
0.0
Retention Alternative Regulator, combines a linear regulator and an ultra-low quiescent regulator for sleep mode in TSMC 55uLPeF
RAR-iLR-qLR-ref-1.62-3.63-0.55-2.5.01_TSMC_55_uLPeF is a Retention Alternating Regulator in TSMC 55uLPeF combining two regulation sub-components: a li...
736
0.0
Retention Alternative Regulator, combines high efficiency in normal mode and ultra-low quiescent current for sleep mode in TSMC 40LP
RAR-eSR-qLR-ref-1.62-3.63-0.55-2.5.02_TSMC_40_LP is a Retention Alternating Regulator in TSMC 40LP embedding two regulation sub-components: a switchin...
737
0.0
Retention Alternative Regulator, combines high efficiency in normal mode and ultra-low quiescent current for sleep mode in TSMC 40uLP
RAR-eSR-qLR-ref-1.62-3.63-0.55-2.5.04g_TSMC_40_uLP is a Retention Alternating Regulator in TSMC 40uLP embedding and controling two ViC regulators call...
738
0.0
Retention Alternative Regulator, combines high efficiency in normal mode and ultra-low quiescent current for sleep mode in TSMC 55uLP
RAR-eSR-qLR-ref-1.62-3.63-0.55-2.5.01_TSMC_55_uLP is a Retention Alternating Regulator in TSMC 55uLP embedding two regulation sub-components: a switch...
739
0.0
Retention Alternative Regulator, combines high efficiency in normal mode and ultra-low quiescent current for sleep mode in TSMC 55uLPeF
RAR-eSR-qLR-ref-1.62-3.63-0.55-2.5.02_TSMC_55_uLPeF is a Retention Alternating Regulator in TSMC 55uLPeF embedding two regulation sub-components: a sw...
740
0.0
eFPGA
Achronix Speedcore™ embedded FPGA (eFPGA) IP includes look-up-table, memory, DSP, and MLP building blocks. Each of these blocks are designed to be mod...
741
0.0
Charge-Pump negative voltage generator with adjustable wide range on SMIC65nm
The present IP is a charge-pump voltage generator developed using SMIC's 65nm ETOX Nor Flash process. It generates high voltages ranging from -10.1V t...
742
0.0
Charge-Pump positive voltage generator with adjustable wide range on SMIC65nm
The present IP is a charge-pump voltage generator developed using SMIC's 65nm ETOX Nor Flash process. It generates high voltages ranging from 3.6V to ...
743
0.0
Charge-Pump positive voltage generator with LDO in-built on SMIC65nm
The present IP is a charge-pump and low dropout voltage generator, which is developed with SMIC 65nm ETOX Nor Flash process. And it generates 4.5~6v h...
744
0.0
AHB to Parallel Bridge for Audio CODEC
dos_AHB_parallel_bridge is a Parallel interface for Codec connection. Support for multiple channels. Each channel includes a FIFO accessible from para...
745
0.0
Chiplet Solution
Based on the traditional advantages of SerDes and DDR IP, KNiulink Semiconductor has launched a solution that meets the UCIe standard based on local r...
746
0.0
PHYIO for PSRAM memory PHY, 1066Mbps
The PHYIOs is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the PSRAM device. The TX is designed to send inf...
747
0.0
AI Accelerator
The accelerator is designed for generic applications to compute 3D tensor convolved by 4D tensor to increase the efficiency by 10x.Marquee created the...
748
0.0
Gigabit Ethernet PHY (1000Base-T)
The DSP-Based GBE IP (development) is a fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-T, 100BASE-TX and 10...
749
0.0
High Speed 132MHz RC oscillator on SMIC40nm
The present IP is a high speed Low Power RC oscillator that developed with SMIC 40nm process. The center frequency of the OSC is 132MHz, it contains 5...
750
0.0
High‑performance 24‑bit, two‑channel PDM‑to‑PCM converter delivering 115 dB SNR with a low‑latency architecture
A high‑performance 24‑bit, two‑channel PDM‑to‑PCM converter delivering 115 dB SNR with a low‑latency architecture designed for responsive, high‑fideli...