Design & Reuse
1153 IP
551
0.118
A/D Converter IP, 10 bits, 300Ksps, UMC 0.35um Logic process
10-Bit 300KSPS single End Analog-to-Digital converter, UMC 0.35um Logic process....
552
0.118
A/D Converter IP, 10 bits, 30Msps, UMC 0.25um Logic process
10-Bit 30MSPS Differential Analog-to-Digital converter, UMC 0.25um Logic process....
553
0.118
A/D Converter IP, 10 bits, 400Ksps, UMC 0.25um Logic process
10-Bit 400KSPS single-end Analog-to-Digital converter, UMC 0.25um Logic process....
554
0.118
A/D Converter IP, 18 bits, 96Ksps, UMC 0.25um Logic process
18-Bit 96KSPS differential Sigma-Delta Analog-to-Digital converter, UMC 0.25um Logic process....
555
0.118
10 bit 1MSPS A/D Converter; UMC 40 nm LP/RVT Low-K Logic Process
10 bit 1MSPS A/D Converter; UMC 40 nm LP/RVT Low-K Logic Process...
556
0.118
10 bit 1MSPS A/D Converter; UMC 40 nm LP/RVT Low-K Logic Process
10 bit 1MSPS A/D Converter; UMC 40 nm LP/RVT Low-K Logic Process...
557
0.118
10 lane FXSLVTX030HH0L bias circuit ; UMC 40nm LP/RVT Logic Process
10 lane FXSLVTX030HH0L bias circuit ; UMC 40nm LP/RVT Logic Process...
558
0.118
10bit 250MSPS Current-steering Video D/A Converter; UMC 0.11um HS/FSG Logic Process
10bit 250MSPS Current-steering Video D/A Converter; UMC 0.11um HS/FSG Logic Process...
559
0.118
40nm LPDDR3-PHY Data block for LightCo ; UMC 40nm LP/LVT Logic Process
40nm LPDDR3-PHY Data block for LightCo ; UMC 40nm LP/LVT Logic Process...
560
0.118
12bit 1MSPS SAR ADC with 8-1 Mux (All C-type) ; UMC 0.13um LL/RVT FSG Logic Process
12bit 1MSPS SAR ADC with 8-1 Mux (All C-type) ; UMC 0.13um LL/RVT FSG Logic Process...
561
0.118
28Gb/s 4 lane high-speed SerDes; UMC 28nm HPC Logic Std/HS process
28Gb/s 4 lane high-speed SerDes; UMC 28nm HPC Logic Std/HS process...
562
0.118
28nm Logic and Mixed-Mode HLP/RVT Process Multi-Voltage BOAC I/O Cell library
28nm Logic and Mixed-Mode HLP/RVT Process Multi-Voltage BOAC I/O Cell library...
563
0.118
28nm Logic and Mixed-Mode HPC/RVT Process Multi-Voltage BOAC I/O Cell library
28nm Logic and Mixed-Mode HPC/RVT Process Multi-Voltage BOAC I/O Cell library...
564
0.118
1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process
1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process...
565
0.118
1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process
1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process...
566
0.118
Band Gap IP, Input: 1.2V - 1.98V, VBG=0.615V, UMC 0.153um Logic process
Input 1.2V-1.98V, VBG=0.615V bandgap, UMC 0.153um Logic process....
567
0.118
Band Gap IP, Input: 2.0V - 3.3V, VBG=1.23V, UMC 0.25um Logic process
VBG=1.23V, VCCAH=3.3V, VCCAH_min=2.0V, Ivccah=25uA, UMC 0.25um Logic process....
568
0.118
Data block of 1:2 DDR2-PHY ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
Data block of 1:2 DDR2-PHY ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...
569
0.118
Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process
Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process...
570
0.118
Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process
Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process...
571
0.118
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process...
572
0.118
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process...
573
0.118
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process...
574
0.118
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process...
575
0.118
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process...
576
0.118
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process...
577
0.118
Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process
Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process...
578
0.118
Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process
Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process...
579
0.118
SATA II PHY IP, Support SATA Gen1 1.5Gb/s and SATA Gen2 3.0Gb/s, UMC 0.18um Logic process
Single channel serial ATA PHY layer compliant with SATA spec. of 3.0Gbps....
580
0.118
RC Oscillator IP, Output: 10KHz, UMC 0.35um Logic process
Sub-low current with external-C, frequency 10KHz, VCCA=2.0V~3.3V, Ivcca<10uA....
581
0.118
RC Oscillator IP, Output: 27.5MHz, UMC 0.35um Logic process
27.5MHz trimmable RC Oscillator, UMC 0.35um Logic process....
582
0.118
RC Oscillator IP, Output: 30KHz - 300KHz, UMC 0.25um Logic process
External-C, frequency 30KHz~300KHz, VCCA=2.0V~3.0V, UMC 0.25um Logic process....
583
0.118
DC-DC IP, Input: 3.3V, Output: +/- 12.5V / +6V, UMC 0.35um Logic process
Three pulse width modulation, boosting voltage from 3.3V to +/-12.5V, and +6V, Ivcca=450uA @ Idrive=0....
584
0.118
DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 0.25um Logic process
Pulse width modulation, boosting voltage from 3.3V to 5V, 50mA driving capability, Ivcca=150uA @ Idrive=0....
585
0.118
PCIE Gen.II PHY; UMC 65nm LP/RVT LowK Logic Process.
PCIE Gen.II PHY; UMC 65nm LP/RVT LowK Logic Process....
586
0.118
ID PAD of OTG USB2.0 ; XIP 55LP/RVT LowK Logic Process
ID PAD of OTG USB2.0 ; XIP 55LP/RVT LowK Logic Process...
587
0.118
DDR1/MDDR PHY CMD/ADDR BLOCK ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process
DDR1/MDDR PHY CMD/ADDR BLOCK ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process...
588
0.118
DDR1/MDDR PHY Data block ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process
DDR1/MDDR PHY Data block ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process...
589
0.118
DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process
DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process...
590
0.118
DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process
DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process...
591
0.118
DDR2 PHY compensation block for 171 series (non BOAC); UMC 0.13um HS/FSG Logic Process
DDR2 PHY compensation block for 171 series (non BOAC); UMC 0.13um HS/FSG Logic Process...
592
0.118
DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process
DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process...
593
0.118
DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process
DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process...
594
0.118
DDR2 PHY Data Block ;UMC 0.13um Logic HS/FSG Process
DDR2 PHY Data Block ;UMC 0.13um Logic HS/FSG Process...
595
0.118
DDR2-PHY command/address block for DRAM chip, BOAC ; UMC 90nm SP/RVT Low-K Logic Process
DDR2-PHY command/address block for DRAM chip, BOAC ; UMC 90nm SP/RVT Low-K Logic Process...
596
0.118
DDR2-PHY compensation block, BOAC; UMC 90nm SP/RVT Low-K Logic process
DDR2-PHY compensation block, BOAC; UMC 90nm SP/RVT Low-K Logic process...
597
0.118
DDR2-PHY data block with BOAC IO; UMC 90nm SP/RVT Lowk Logic Process
DDR2-PHY data block with BOAC IO; UMC 90nm SP/RVT Lowk Logic Process...
598
0.118
DDR2/3 Combo Command /Address Block (with 2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Process
DDR2/3 Combo Command /Address Block (with 2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Process...
599
0.118
DDR2/3 COMBO Compensation block (2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Porcess
DDR2/3 COMBO Compensation block (2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Porcess...
600
0.118
DDR2/3 PHY Combo PHY data block (1.0v SP & 2.5V device); UMC 90nm SP/RVT LowK Logic Process
DDR2/3 PHY Combo PHY data block (1.0v SP & 2.5V device); UMC 90nm SP/RVT LowK Logic Process...