Design & Reuse
Catalog of SIP Cores
System on Chip design resources
1577 IP
1
0.0
40G UDP IP Stack
Logic Fruit’s 40G UDP IP Stack implements a hardware protocol stack for UDP/IP, allowing fast communication over a point-to-point connection or LAN....
2
0.0
10G UDP IP Stack
This 10G UDP IP Stack carries out the implementation of a hardware protocol stack for UDP/IP, allowing fast communication over a point-to-point connec...
3
0.0
CAN Controller
CAN Controller...
4
0.0
PCIe GEN6 PHY
Designed for next-generation PCIe systems, the PCIe GEN6 PHY IP supports data rates up to 64GT/s per lane with advanced PAM4 signaling. It ensures eff...
5
0.0
AES 256 encryption IP core
Logic Fruit’s AES 256 encryption IP core implements Rijndael encoding and decoding. It works with 256-bit blocks and is programmed to work with 256-bi...
6
0.0
JESD204B Transmitter and Receiver
Logic fruit Technologies has designed JESD204B RTL IP. It can support increased lane rates upto 12.5Gbps for higher bandwidth applications. It can be ...
7
0.0
JESD204C Transmitter and Receiver
Logic fruit Technologies has designed JESD204C RTL IP to support increased lane rates upto 32Gbps for higher bandwidth applications. This IP can be co...
8
0.0
1G UDP IP Stack
Logic Fruit’s 1G UDP IPⓇ is specialized in data transmission and reception over the internet. The UDP Protocol helps to establish a low-latency and lo...
9
0.0
MIL1553B IP Core
MIL-STD-1553B defines specifications for terminal device operation and coupling, word structure and format, messaging protocol and electrical characte...
10
0.0
MIL1553B IP Core
MIL-STD-1553B defines specifications for terminal device operation and coupling, word structure and format, messaging protocol and electrical characte...
11
0.0
LIN Master Slave Controller
Local Interconnect Network (LIN) is a broadcasting, Single Master, and Multi Slave (up to 16) communication protocol designed to support those feature...
12
0.0
DisplayPort Transmitter & Receiver
Logic Fruit Technologies has designed & implemented DISPLAY PORT Transmitter & Receiver IP Cores supporting multiple line rates up to 8.1Gbps. The IP ...
13
0.0
FlexRay Controller
Logic Fruit Technologies has designed FlexRay RTL IP Core, supporting data rate up to 10 Mbps. FlexRay, a high-speed protocol for advanced vehicles...
14
0.0
Logic Fruit Technologies - SoC design services
Based in Gurgaon, India, Logic Fruit Technologies designs and deploys embedded solutions for customers around the world. The company has specific expe...
15
0.0
FPGA Proven PCIe GEN6 Controller
PCIe GEN6 Controller IP Delivers data speed up to 64GT/s (Gigatransfers per second) per lane. Multi-channel packet processing and enhanced RAS capabil...
16
0.0
CPRI Master and Slave
CPRI is a high-speed serial interface for network radio equipment controllers (REC) to receive and provide data to remote Radio Equipment (RE)....
17
0.0
ARINC 818 Transmitter & Receiver
Logic Fruit Technologies has designed & implemented ARINC 818-2 Transmitter & Receiver IP Core supporting multiple line rates up to 8.5 Gbps....
18
0.0
ETHERNET 10G MAC
The 10G Ethernet MAC core is a thoroughly verified Ethernet Media Access Controller function that interfaces with physical layer devices in an Etherne...
19
0.0
Multichannel module supporting ARINC429 Receiver/Transmitter
ARINC 429 IP Core is a multichannel module with support for virtually any number of transmitters and Receivers....
20
20.0
MAXVY MIPI CSI2 Receiver IP
The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile...
21
20.0
MAXVY MIPI DSI-2 Transmitter Interface IP
MIPI DSI-2 (Display Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile dev...
22
10.0
MAXVY Technologies
MAXVY is a fast growing fabless semiconductor company which is currently engaged in the fields of RTL design and Verification IP Solutions. We offe...
23
10.0
Expanded Serial Peripheral Interface (xSPI) Slave Controller
The MAXVY's JESD251 Expanded Serial Peripheral Interface Slave controller is provides high data throughput, low signal count, and limited backward com...
24
8.0
MAXVY Universal Chiplet Interconnect Express (UCIe) Verification IP
MAXVY UCIe VIP , a state-of-the-art solution that offers a comprehensive set of features and capabilities to ensure the quality and performance of you...
25
8.0
MIPI I3C Verification IP
The Maxvy's MIPI-I3C VIP provides configurable option to select I3C master/secondary master/slave based on the MIPI I3C DUT function as per user speci...
26
5.0
DDR5 CKD 01 - Clock Driver
MAXVY DDR5CKD01 is a high-performance FPGA-proven registering clock driver designed for DDR5 CUDIMM, CSODIMM, and CAMM applications, providing relia...
27
5.0
DDR5 Power Management IC
Power Management IC (PMIC) is designed for DDR5 RDIMM, DDR5 LRDIMM, DDR5 NVDIMM application. PMIC is used for switching and LDO regulators. PMIC-I3C I...
28
5.0
DDR5 REGISTERING CLOCK DRIVER (RCD) IP - DDR5RCD03
The DDR5RCD03 is a registering clock driver used on DDR5 RDIMMs and LRDIMMs. Its primary function is to buffer the Command/Address (CA) bus, chip sele...
29
5.0
DDR5 Serial Presence Detect (SPD5) Hub Interface
The SPD5 Hub Function IP has been developed to interface I3C/I2C Host Bus and it allows an isolation of local devices like Temperature Sensor(TS), fro...
30
5.0
DDR5 Temperature Sensor - TS5111 and TS5110
he TS5111 and TS5110 device incorporate thermal sensing capability which is controlled and read over two wire bus. These device operate on I2C and I3C...
31
5.0
MIPI I3C Master RISC-V based subsystem
RISC-V based MAXVY MIPI I3C master interface has been developed to ease sensor system design architectures in mobile wireless products by providing a ...
32
5.0
MIPI-I3C COMBINED IP HOST/TARGET IP
The MAXVY MIPI I3C Controller IP (Host/Target) is a high-performance, standards-compliant solution for efficient multi-sensor integration in mobile,...
33
2.0
MIPI A-PHY Verification IP
MIPI A-PHY v1.0 is a physical layer communication protocol designed for automotive applications, including driver assistance, autonomous driving, and ...
34
1.0
MIPI SPMI Target Controller
The System Power Management Interface is a two wire interface that connects the integrated power controller (PC) of a System-on-Chip (SoC) processor s...
35
0.0
MAXVY AHB Verification IP
Maxvy AHB Verification IP provides a complete solution for Verification of AMBA 3.0 AHB-Lite protocol v1.0 component of a SOC or ASIC. Maxvy AHB-Lite ...
36
0.0
MAXVY AXI Verification IP
The MAXVY'S AMBA-AXI VIP provides a complete solution for verification of AMBA-AXI protocol version 2.0. MAXVY’S AXI verification IP is fully compatib...
37
0.0
MAXVY CPRI verification IP
MAXVY provides configurable CPRI TX/RX verification IP. MAXVY's CPRI verification IP is fully compatible with CPRI version v7.0 with backward compatib...
38
0.0
MAXVY EXPANDED SERIAL PERIPHERAL INTERFACE (XSPI) HOST CONTROLLER IP
MAXVY’s Expanded Serial Peripheral Interface (xSPI) Host Controller IP, compliant with JEDEC JESD251, is a high-performance, low-pin-count controlle...
39
0.0
MAXVY MIPI CSI -2 TRANSMITTER IP -V3
MIPI CSI-2 (Camera Serial Interface) Transmitter IP defines an interface between a peripheral device (camera) and host processor (application engine) ...
40
0.0
MAXVY MIPI D-PHY Receiver IP
The MAXVY MIPI D-PHY Receiver IP is a robust high-speed PHY solution designed for receiving MIPI data streams in advanced imaging, display, automoti...
41
0.0
MAXVY MIPI D-PHY Transmitter IP
The MAXVY MIPI D-PHY Transmitter IP is a high-performance PHY solution designed for transmitting high speed data in modern display, camera, automotiv...
42
0.0
MAXVY MIPI DSI-2 RX Controller IP
The MAXVY's MIPI DSI-2 RX Controller IP is a fully compliant receive solution designed to interface with MIPI DSI-2 transmitters and deliver display d...
43
0.0
MAXVY MIPI I3C MASTER (SDR) IP
The Maxvy MIPI I3C Master (SDR) RTL IP is a lightweight, FPGA-validated controller compliant with the MIPI I3C public release specification, designe...
44
0.0
MAXVY MIPI I3C TARGET IP
MAXVY MIPI I3C Slave SDR RTL Design IP is a fully compliant I3C target interface solution enabling high bandwidth, low-pin-count sensor connectivity ...
45
0.0
MAXVY MIPI SPMI HOST CONTROLLER
The System Power Management Interface is a two wire interface that connects the integrated power controller (PC) of a System-on-Chip (SoC) processor s...
46
0.0
MAXVY’S OCTAL SERIAL PERIPHERAL INTERFACE (OSPI) TARGET IP
MAXVY’s Octal Serial Peripheral Interface (OSPI) Target IP is a high-bandwidth memory interface solution designed for next-generation non-volatile m...
47
0.0
MAXVY’S QUAD SERIAL PERIPHERAL INTERFACE (QSPI) TARGET IP
MAXVY’s Quad Serial Peripheral Interface (QSPI) Target IP is a high-performance, scalable interface solution designed for seamless integration with ...
48
0.0
RISC V - CORE DEVELOPMENT
RISC-V (pronounced risk-five ) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015...
49
4.0
32 bit 8Ksps sigma delta ADC for Seismic Precision application in TSMC 180nm
32-bit delta sigma analog-to-digital converter (ADC) containing a low noise programmable gain amplifier (PGA) and 2 channel input multiplexers. This A...
50
4.0
12b 5Msps ADC for microcontroller business in UMC 40nm
AD12BSAR5M40LP is a 12-bit Successive Approximation Analog-to-Digital Converter (ADC) that operates up to 5MS/s. The ADC has excellent linearity with ...