Design & Reuse
Catalog of SIP Cores
System on Chip design resources
1577 IP
951
0.118
D/A Converter IP, 10 bits, 1MHz, UMC 0.153um Logic process
10-Bit 1MHz Voltage Output R-2R Digital-to-Analog converter, UMC 0.153um Logic process....
952
0.118
D/A Converter IP, 10 bits, 2.5Msps, HJTC 0.18um Logic process
10-Bit 2.5MSPS current Digital-to-Analog converter, HJ 0.18um Logic process....
953
0.118
D/A Converter IP, 16 bits, 96Ksps, UMC 0.25um Logic process
16-Bit 96KSPS voltage output stereo-line Digital-to-Analog converter, UMC 0.25um Logic process....
954
0.118
A/D Converter IP, 10 bits, 300Ksps, UMC 0.35um Logic process
10-Bit 300KSPS single End Analog-to-Digital converter, UMC 0.35um Logic process....
955
0.118
A/D Converter IP, 10 bits, 30Msps, UMC 0.25um Logic process
10-Bit 30MSPS Differential Analog-to-Digital converter, UMC 0.25um Logic process....
956
0.118
A/D Converter IP, 10 bits, 400Ksps, UMC 0.25um Logic process
10-Bit 400KSPS single-end Analog-to-Digital converter, UMC 0.25um Logic process....
957
0.118
A/D Converter IP, 18 bits, 96Ksps, UMC 0.25um Logic process
18-Bit 96KSPS differential Sigma-Delta Analog-to-Digital converter, UMC 0.25um Logic process....
958
0.118
10 bit 1MSPS A/D Converter; UMC 40 nm LP/RVT Low-K Logic Process
10 bit 1MSPS A/D Converter; UMC 40 nm LP/RVT Low-K Logic Process...
959
0.118
10 bit 1MSPS A/D Converter; UMC 40 nm LP/RVT Low-K Logic Process
10 bit 1MSPS A/D Converter; UMC 40 nm LP/RVT Low-K Logic Process...
960
0.118
10 lane FXSLVTX030HH0L bias circuit ; UMC 40nm LP/RVT Logic Process
10 lane FXSLVTX030HH0L bias circuit ; UMC 40nm LP/RVT Logic Process...
961
0.118
10bit 250MSPS Current-steering Video D/A Converter; UMC 0.11um HS/FSG Logic Process
10bit 250MSPS Current-steering Video D/A Converter; UMC 0.11um HS/FSG Logic Process...
962
0.118
40nm LPDDR3-PHY Data block for LightCo ; UMC 40nm LP/LVT Logic Process
40nm LPDDR3-PHY Data block for LightCo ; UMC 40nm LP/LVT Logic Process...
963
0.118
12bit 1MSPS SAR ADC with 8-1 Mux (All C-type) ; UMC 0.13um LL/RVT FSG Logic Process
12bit 1MSPS SAR ADC with 8-1 Mux (All C-type) ; UMC 0.13um LL/RVT FSG Logic Process...
964
0.118
28Gb/s 4 lane high-speed SerDes; UMC 28nm HPC Logic Std/HS process
28Gb/s 4 lane high-speed SerDes; UMC 28nm HPC Logic Std/HS process...
965
0.118
28nm Logic and Mixed-Mode HLP/RVT Process Multi-Voltage BOAC I/O Cell library
28nm Logic and Mixed-Mode HLP/RVT Process Multi-Voltage BOAC I/O Cell library...
966
0.118
28nm Logic and Mixed-Mode HPC/RVT Process Multi-Voltage BOAC I/O Cell library
28nm Logic and Mixed-Mode HPC/RVT Process Multi-Voltage BOAC I/O Cell library...
967
0.118
1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process
1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process...
968
0.118
1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process
1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process...
969
0.118
Band Gap IP, Input: 1.2V - 1.98V, VBG=0.615V, UMC 0.153um Logic process
Input 1.2V-1.98V, VBG=0.615V bandgap, UMC 0.153um Logic process....
970
0.118
Band Gap IP, Input: 2.0V - 3.3V, VBG=1.23V, UMC 0.25um Logic process
VBG=1.23V, VCCAH=3.3V, VCCAH_min=2.0V, Ivccah=25uA, UMC 0.25um Logic process....
971
0.118
Data block of 1:2 DDR2-PHY ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
Data block of 1:2 DDR2-PHY ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...
972
0.118
Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process
Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process...
973
0.118
Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process
Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process...
974
0.118
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process...
975
0.118
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process...
976
0.118
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process...
977
0.118
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process...
978
0.118
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process...
979
0.118
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process...
980
0.118
Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process
Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process...
981
0.118
Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process
Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process...
982
0.118
SATA II PHY IP, Support SATA Gen1 1.5Gb/s and SATA Gen2 3.0Gb/s, UMC 0.18um Logic process
Single channel serial ATA PHY layer compliant with SATA spec. of 3.0Gbps....
983
0.118
RC Oscillator IP, Output: 10KHz, UMC 0.35um Logic process
Sub-low current with external-C, frequency 10KHz, VCCA=2.0V~3.3V, Ivcca<10uA....
984
0.118
RC Oscillator IP, Output: 27.5MHz, UMC 0.35um Logic process
27.5MHz trimmable RC Oscillator, UMC 0.35um Logic process....
985
0.118
RC Oscillator IP, Output: 30KHz - 300KHz, UMC 0.25um Logic process
External-C, frequency 30KHz~300KHz, VCCA=2.0V~3.0V, UMC 0.25um Logic process....
986
0.118
DC-DC IP, Input: 3.3V, Output: +/- 12.5V / +6V, UMC 0.35um Logic process
Three pulse width modulation, boosting voltage from 3.3V to +/-12.5V, and +6V, Ivcca=450uA @ Idrive=0....
987
0.118
DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 0.25um Logic process
Pulse width modulation, boosting voltage from 3.3V to 5V, 50mA driving capability, Ivcca=150uA @ Idrive=0....
988
0.118
PCIE Gen.II PHY; UMC 65nm LP/RVT LowK Logic Process.
PCIE Gen.II PHY; UMC 65nm LP/RVT LowK Logic Process....
989
0.118
ID PAD of OTG USB2.0 ; XIP 55LP/RVT LowK Logic Process
ID PAD of OTG USB2.0 ; XIP 55LP/RVT LowK Logic Process...
990
0.118
DDR1/MDDR PHY CMD/ADDR BLOCK ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process
DDR1/MDDR PHY CMD/ADDR BLOCK ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process...
991
0.118
DDR1/MDDR PHY Data block ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process
DDR1/MDDR PHY Data block ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process...
992
0.118
DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process
DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process...
993
0.118
DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process
DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process...
994
0.118
DDR2 PHY compensation block for 171 series (non BOAC); UMC 0.13um HS/FSG Logic Process
DDR2 PHY compensation block for 171 series (non BOAC); UMC 0.13um HS/FSG Logic Process...
995
0.118
DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process
DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process...
996
0.118
DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process
DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process...
997
0.118
DDR2 PHY Data Block ;UMC 0.13um Logic HS/FSG Process
DDR2 PHY Data Block ;UMC 0.13um Logic HS/FSG Process...
998
0.118
DDR2-PHY command/address block for DRAM chip, BOAC ; UMC 90nm SP/RVT Low-K Logic Process
DDR2-PHY command/address block for DRAM chip, BOAC ; UMC 90nm SP/RVT Low-K Logic Process...
999
0.118
DDR2-PHY compensation block, BOAC; UMC 90nm SP/RVT Low-K Logic process
DDR2-PHY compensation block, BOAC; UMC 90nm SP/RVT Low-K Logic process...
1000
0.118
DDR2-PHY data block with BOAC IO; UMC 90nm SP/RVT Lowk Logic Process
DDR2-PHY data block with BOAC IO; UMC 90nm SP/RVT Lowk Logic Process...