Design & Reuse
Catalog of SIP Cores
System on Chip design resources
1577 IP
201
3.0
Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in GF 28SLP process
TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
202
3.0
Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 28HPC process
TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
203
3.0
Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 55LP process
TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
204
3.0
Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 65GP process
TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
205
3.0
Single Lane and Quad Lane 8Gbps PCIe3.0 PHY in Samsung 28LPP process
TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
206
3.0
Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in GF 28SLP process
TERMINUS-CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single &Quad-Lane PCI Express PHY that supports PCI Express protocol and...
207
3.0
Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in TSMC 28HPC process
TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
208
3.0
Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in TSMC 65G process
TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
209
3.0
MIPI 4.1 M-PHY HS Gear 4
MIPI M-PHY HS Gear 4 IP is compliant with the MIPI serial communication protocol for use in mobile systems where performance, power, and efficiency ar...
210
3.0
Low Jitter 1.25GHz to 2.5GHz Quadrature Output PLL
Terminus Circuits offers High speed, low Jitter PLL with 1.25GHz to 2.5GHz output. The ring oscillator based PLL provides balanced quadrature output. ...
211
3.0
Multi-Link Multi-Protocol SerDes 10Gbps in GF 28SLP
Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SA...
212
3.0
Multi-Link Multi-Protocol SerDes 10Gbps in TSMC 55LP
Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SA...
213
3.0
Multi-Link Multi-Protocol SerDes 10Gbps in TSMC 65GP
Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SA...
214
3.0
Multi-Link Multi-Protocol SerDes 16Gbps in TSMC 28HPC
Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SA...
215
2.0
Process Voltage Temperature (PVT) Sensor Subsystem
The monitoring of process, voltage and temperature variations are critical to optimize power and performance for modern SoCs/ASICs, especially for adv...
216
1.0
6MHz ±1% PVT 1.8V Low Power Oscillator in Silterra 0.18um
This macro-cell is a low-power, precision, general purpose 1.8V 6MHz ±1% PVT internal oscillator core aimed for clock generation. A 7 bit digital bus ...
217
1.0
6MHz ±1% PVT 3.3V Low Power Oscillator in Silterra 0.18um
This macro-cell is a low-power, precision, general purpose 3.3V 6MHz ±1% PVT internal oscillator core aimed for clock generation. A 7 bit digital bus ...
218
1.0
PVT Sensor
The PVT sensor indicates the junction temperature as a 12-bit binary digital code. It contains a main sensor, remote probes and an Analog-to-Digital C...
219
0.3729
LVDS Combo with PVT Compensation - TSMC 12nm 12FFC,FFC+
Dolphin s interface IP for standard I/O and specialty I/O delivers ultra high performance for DDRx4, LPDDRx, DDR PHY, LVDS, LVPECL, I2C, PCI, SerDes, ...
220
0.3729
LVDS Combo with PVT Compensation - TSMC 16nm 16FFC,FF
Dolphin s interface IP for standard I/O and specialty I/O delivers ultra high performance for DDRx4, LPDDRx, DDR PHY, LVDS, LVPECL, I2C, PCI, SerDes, ...
221
0.0
10G Base T Ethernet PHY
Terminus Circuits presents a state-of-the-art Ethernet PHY IP, supporting 100 Mbps, 1 Gbps, and 10 Gbps data rates. Purpose-built for performance-driv...
222
0.0
Terminus Circuits - Design services, interconnect solutions
Terminus Circuits offers High Speed Serial Link Interface IPs and provides interconnect solutions across many standards like USB.org, PCIe-SIG, IEEE, ...
223
0.0
PVT Sensor - TSMC 12 FFC
1-VIA’s PVT Sensor is a highly integrable macro for monitoring process, voltage and temperature variation on-chip. It consumes ultra-low power in miss...
224
0.0
PVT Sensor - TSMC 16 FFC
1-VIA’s PVT Sensor is a highly integrable macro for monitoring process, voltage and temperature variation on-chip. It consumes ultra-low power in miss...
225
0.0
PVT Sensor - TSMC 28 HPC+
1-VIA’s PVT Sensor is a highly integrable macro for monitoring process, voltage and temperature variation on-chip. It consumes ultra-low power in miss...
226
0.0
PVT Sensor - TSMC 40
1-VIA’s PVT Sensor is a highly integrable macro for monitoring process, voltage and temperature variation on-chip. It consumes ultra-low power in miss...
227
0.0
PVT Sensor - TSMC 7FF
1-VIA’s PVT Sensor is a highly integrable macro for monitoring process, voltage and temperature variation on-chip. It consumes ultra-low power in miss...
228
0.0
PVT sensor in 28nm
Process voltage and temperature detection of the silicon chip die is accomplished by PVT Sensor, an IP. It offers special characteristics like tempera...
229
0.0
PVT sensor integrated SAR ADC in 12nm
PVT Sensor & SAR ADC is an IP Core including TEMSEN ,.SARADC and 3xPOR. The SAR ADC used in this system offers a 10-bit resolution, ensuring precise a...
230
0.0
PVT Sensor(SF 4nm, LN04LPP)
The PVT sensor indicates the junction temperature as a 12-bit binary digital code. It contains a main sensor, remote probes and an Analog-to-Digital...
231
200.0
Post-Quantum Cryptography - xQlave® PQC ML-KEM (Kyber)
In a world where advances in quantum computing threaten traditional cryptographic systems, Xiphera’s xQlave® ML-KEM (Kyber) Key Encapsulation Mechanis...
232
130.0
LPDDR6, LPDDR5X Combo PHY & Controller
INNOSILICON™ introduces its LPDDR6/5X PHY and Controller IP, purpose-built for the AI era’s high-performance chip design needs. This solution is fully...
233
105.0
CME IoT platform
Sensor-Mate (sensing node)Long distance wireless communication (920MHz)Sensor-Gateway (Aggregator)920MHz wireless module (CM Engineering proprietary)G...
234
100.0
MACsec - Extreme-speed - Security Protocol
MACsec is a point-to-point protocol located on layer two (Data Link) of the OSI model. Xiphera's comprehensive MACsec solution portfolio safeguards th...
235
100.0
PCIe 5.0 PHY & Controller
The Innosilicon Gen1/2/3/4/5 PCI Express Controller provides a PCI Express Root Complex (RC) and Endpoint (EP) application. It’s a high performance, h...
236
100.0
Post-Quantum Cryptography - nQrux® Secure Boot - Quantum-Secure Authenticated Boot (PQC)
nQrux® Secure Boot enhances system security by enabling quantum-secure authenticated boot, crucial for verifying the authenticity and integrity of bin...
237
100.0
Post-Quantum Cryptography - xQlave® PQC ML-DSA (Dilithium)
The xQlave® ML-DSA (Dilithium) Digital Signature Algorithm IP core secures critical infrastructures and operations against the threat of quantum compu...
238
100.0
LPDDR5X, LPDDR5, LPDDR4X, LPDDR4 Combo PHY & Controller
The INNOSILICON™ LPDDR IP includes a LPDDR5X/5/4X/4 Combo PHY and controller. It is fully compliant with the JEDEC standard. Optimized for low-power a...
239
80.0
GDDR7 PHY & Controller
The INNOSILICON™ GDDR7 PHY is fully compliant with the JEDEC GDDR7 standard, supporting data rates of up to 32 Gbps in PAM3 mode. In PAM3 mode, each b...
240
60.0
UCIe Chiplet PHY & Controller
INNOSILICON™ UCIe Chiplet IP offers a customizable solution for seamless, low-latency data transfer between silicon dies and chips, enabling heterogen...
241
51.0
TLS 1.3 - Security Protocol
Transport Layer Security (TLS) is a cryptographic protocol used for building a secure connection between a client and a server over the Internet. A ha...
242
51.0
True Random Number Generator (TRNG)
The TRNG IP core establishes a benchmark for hardware-based security in cryptographic systems, by generating high-entropy, true random numbers essenti...
243
50.0
AES - GCM - Extreme-speed variant
XIP1113E is a an extreme-speed IP core implementing the Advanced Encryption Standard (AES) in Galois Counter Mode (GCM). AES-GCM is a widely used cryp...
244
50.0
IPsec - Security Protocol
IPsec (Internet Protocol Security) is a widely implemented protocol to secure communications across the Internet. Xiphera’s IPsec core enhances secure...
245
48.0
nQrux® Crypto Module
Xiphera’s nQrux® Crypto Module IP core provides a comprehensive security platform that allows for customisation of top-notch cryptographic services, s...
246
43.0
Elliptic Curve Cryptography (ECC) Accelerator
The high-speed ECC Accelerator reaches to more than a thousand operations per second in a modern FPGA or ASIC. Furthermore, it covers all NIST P curve...
247
25.0
HBM4, HBM3E PHY & Controller
INNOSILICON™ HBM4/3E IP is fully compliant with the JEDEC standard for HBM3E and the preliminary specification for HBM4. The IP includes a customizabl...
248
25.0
DDR5, DDR4 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal DDR5/4 Combo PHY s provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDR...
249
15.0
GDDR6X, GDDR6 Combo PHY & Controller
The INNOSILICON™ GDDR6X/6 PHY is fully compliant with the JEDEC GDDR6X/6 standard, supporting data rates of up to 20 Gbps per pin for PAM2 GDDR6 mode ...
250
3.0
Pseudorandom Number Generator (PRNG) - Balanced variant
The PRNG IP core establishes a benchmark for hardware-based security in cryptographic systems by generating high-quality pseudorandom numbers. It deli...