Design & Reuse
808 IP
551
0.0
MIPI CSI-2 TX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
552
0.0
MIPI D-PHY Combo LVDS CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2, MIPI D-PHY, and LVDS protocols. The CSI-2 link protocol specification is a part of group of communication...
553
0.0
MIPI D-PHY Combo LVDS DSI TX IP
Innosilicon MIPI DSI Transmitter implements DSI, MIPI D-PHY, and LVDS protocol. The DSI link protocol specification is a part of group of communicatio...
554
0.0
MIPI D-PHY CSI-2 RX IP
Innosilicon CSI-2 Receiver implements MIPI CSI-2 protocol as well as D-PHY protocol. The CSI-2 link protocol specification is a part of group of commu...
555
0.0
MIPI D-PHY DSI 1.2G RX IP
Innosilicon MIPI DSI receiver implements the MIPI DSI as well as D-PHY protocols. The DSI link protocol specification is a part of group of communicat...
556
0.0
MIPI D-PHY DSI 1.5G RX IP
Innosilicon MIPI DSI RX IP implements the MIPI D-PHY as well as MIPI DSI protocols. The DSI link protocol specification is a part of group of communic...
557
0.0
MIPI D-PHY DSI TX IP
Innosilicon MIPI DSI Transmitter implements the DSI protocol as well as MIPI D-PHY protocol. The DSI link protocol specification is a part of group of...
558
0.0
MIPI D-PHY TX
The Innosilicon MIPI D-PHY TX provides a MIPI® high speed data plus low-power low speed transmitter that supports data transfer in the bi-directional ...
559
0.0
MIPI D-PHY TX COMBO LVDS PHY
The Innosilicon MIPI D-PHY TX combo LVDS PHY integrates a D-PHY and a LVDS in a single IP core, which provides a MIPI® high speed data plus low-power ...
560
0.0
MIPI D-PHY TX Combo TTL PHY
The Innosilicon MIPI D-PHY TX provides a MIPI® high speed data plus low-power low speed transmitter that supports data transfer in the bi-directional ...
561
0.0
MIPI D-PHY_1.2G CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
562
0.0
MIPI D-PHY_1.5G CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
563
0.0
MIPI D-PHY_2.5G CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
564
0.0
MIPI D-PHY_4.5G CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
565
0.0
MIPI DPHY DSI TX IP
Innosilicon MIPI DSI Transmitter implements the DSI protocol as well as MIPI D-PHY protocol. The DSI link protocol specification is a part of group of...
566
0.0
MIPI DPHY1.2 RX (support combo TTL, LVDS, HiSPI)
The Innosilicon MIPI D-PHY IP provides D-PHY in a single IP core. It integrates a compatible PHY that supports high speed data receiver, plus a MIPI® ...
567
0.0
MIPI DPHY2.0/CPHY1.1 TX (support combo TTL, LVDS, HiSPI)
The Innosilicon MIPI C/D PHY TX integrates a MIPI C-PHY and a MIPI D-PHY in a single IP core, which provides a MIPI high speed data plus low-power low...
568
0.0
MIPI DSI-2 DSC RX IP
Innosilicon MIPI DSI-2 DSC RX IP implements the MIPI C/D-PHY as well as MIPI DSI-2 protocols and contains the DSC (Display Stream Compression) algorit...
569
0.0
MIPI M-PHY
INNOSILICON™ M-PHY IP implements the MIPI M-PHY protocol V4.1. The M-PHY protocol specification is a part of a group of communication protocols define...
570
0.0
Discrete Cosine Transform OL_DCT
This core can perform the two dimensional Discrete Cosine Transform (DCT) and its inverse (IDCT) on an 8x8 block of samples. The simple, fully synchro...
571
0.0
NIST P-224/P-256/P-384/P521 ECDH and ECDSA
The NIST P-224/P-256/P-384/P-521 ECDH and ECDSA can be used for elliptic curve key generation, computation of Diffie-Hellman shared secrets as well as...
572
0.0
DLL
The INNOSILICON™ Delay-Locked Loop (DLL) PHY is a mix-signal circuit used in low-power and high-speed applications to align and synchronize clock sign...
573
0.0
PLL
INNOSILICON™ PLL IP is a high-speed, low-jitter frequency synthesizer, developed to reduce time-to-market, risk, and design cost. It can generate a st...
574
0.0
VLSI Plus - ISP Design Services and Engineering Services
VLSI Plus team of image processing professional, experienced in the definition and efficient VLSI implementation of high image quality ISP (Image Si...
575
0.0
OL_H264E-CFS HDTV H.264/AVC Video Encoder with Compressed Frame Store
The OL_H264E-CFS core is a hardware implementation of the H.264 video compression algorithm. The core accepts up to the highest resolution HDTV video ...
576
0.0
eMMC/SD/SDIO PHY & Controller
INNOSILICON™ eMMC/SD/SDIO Combo IP is a comprehensive solution designed to support high-performance storage and I/O connectivity for a wide range of a...
577
0.0
In-memory computing
CompuRAM™ provides In Memory Computing (IMC) that will enable solutions for computing at the Edge to be more power efficient. At present, sensor data ...
578
0.0
Analog Mixed-Signal and RFIC design service
Engage with customer in all stages of design from feasibility study, architecture modeling and sim, circuit and layout design, to evaluation. RF IC...
579
0.0
ONFI
INNOSILICON™ ONFI IP provides a connectivity solutions for ICs requiring access to ONFI-compatible NAND Flash devices. Optimized for low-power and hig...
580
0.0
INNOLINK Chiplet PHY&Controller
Innosilicon INNOLINK™ IP provides a leading-edge chiplet solution allowing massive amounts of low-latency data to pass seamlessly between smaller chi...
581
0.0
INNOLINK-B Controller
The INNOLINK Controller (ILC) combined with INNOLINK PHY is a complete solution for high speed data communication between dies or chips. INNOLIN, GDDR...
582
0.0
INNOLINK-B PHY
Innosilicon can provide different Die2Die solution for customer depend on package type, Following is Innosilicon Die2Die IP family: Innolink-A, Serde...
583
0.0
INNOLINK-C Controller
The INNOLINK-C Controller (hereinafter referred to as “ILC”) combined with INNOLINK-C PHY is a complete solution for high-speed data communication bet...
584
0.0
INNOLINK-C PHY
Innosilicon can provide different Die-to-Die and Chip-to-Chip solutions for customer according to package types. The followings are Innosilicon Die-to...
585
0.0
Innovative Ultra-High-Speed Chiplet Solution
Innosilicon INNOLINK™ IP provides a leading-edge chiplet solution allowing massive amounts of low-latency data to pass seamlessly between smaller chip...
586
0.0
Low Power Mono Audio CODEC_1ADC1DAC
Innosilicon Audio Codec IP is a low power, high resolution, mono CODEC solution which employs Sigma-Delta noise-shaping technique. The ADC, DAC and po...
587
0.0
Low Power Stereo Audio CODEC
Innosilicon Codec is a low power, high resolution, stereo CODEC solution which employs Sigma-Delta noise-shaping technique. The ADC, DAC and power amp...
588
0.0
Low Power Stereo Audio CODEC_2ADC1DAC
Innosilicon Codec is a low power, high resolution, stereo CODEC solution which employs Sigma-Delta noise-shaping technique. The ADC, DAC and power amp...
589
0.0
Low Power Stereo Audio CODEC_2ADC2DAC
Innosilicon Codec is a low power, high resolution, stereo CODEC solution which employs Sigma-Delta noise-shaping technique. The ADC, DAC and power amp...
590
0.0
Low Power Stereo Audio CODEC_4ADC4DAC
Innosilicon Codec is a low power, high resolution, stereo CODEC solution which employs Sigma-Delta noise-shaping technique. The ADC, DAC and power amp...
591
0.0
Low Power Stereo Audio CODEC_80db
Innosilicon Codec is a low power, stereo CODEC solution which employs Sigma-Delta noise-shaping technique. The ADC, DAC and power amplifier are integr...
592
0.0
Low Power Stereo Audio CODEC_90dB
Innosilicon Codec is a low power, high resolution, stereo CODEC solution which employs Sigma-Delta noise-shaping technique. The ADC, DAC and power amp...
593
0.0
Power-On-Reset IP
INNOSILICON™ Power-On-Reset (POR) IP provides reliable reset functions for a variety of applications. It is powered by an analog supply and monitors b...
594
0.0
DP/eDP PHY + Controller
INNOSILICON™ DP/eDP IP is designed for transmitting or receiving video and audio signals between the video source devices and display devices. It is f...
595
0.0
DP1.1 RX PHY
Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. ...
596
0.0
DP1.2 RX PHY
Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. ...
597
0.0
DP1.2 Transmitter PHY
Innosilicon DP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications. In...
598
0.0
DP1.2 Transmitter PHY_40nm
Innosilicon DP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications. In...
599
0.0
DP1.4 Receiver Controller
This document describes the low power Innosilicon DP 1.4 Receiver controller, which is fully compliant with DP 1.4 specification and eDP 1.4 standard....
600
0.0
DP1.4 TX PHY
Innosilicon eDP TX PHY is designed to transmit video, audio, and auxiliary data from a system host device to a display device for display applications...