Design & Reuse
Catalog of SIP Cores
System on Chip design resources
796 IP
201
0.0
PVT Sensor - TSMC 28 HPC+
1-VIA’s PVT Sensor is a highly integrable macro for monitoring process, voltage and temperature variation on-chip. It consumes ultra-low power in miss...
202
0.0
PVT Sensor - TSMC 40
1-VIA’s PVT Sensor is a highly integrable macro for monitoring process, voltage and temperature variation on-chip. It consumes ultra-low power in miss...
203
0.0
PVT Sensor - TSMC 7FF
1-VIA’s PVT Sensor is a highly integrable macro for monitoring process, voltage and temperature variation on-chip. It consumes ultra-low power in miss...
204
0.0
PVT sensor in 28nm
Process voltage and temperature detection of the silicon chip die is accomplished by PVT Sensor, an IP. It offers special characteristics like tempera...
205
0.0
PVT sensor integrated SAR ADC in 12nm
PVT Sensor & SAR ADC is an IP Core including TEMSEN ,.SARADC and 3xPOR. The SAR ADC used in this system offers a 10-bit resolution, ensuring precise a...
206
0.0
PVT Sensor(SF 4nm, LN04LPP)
The PVT sensor indicates the junction temperature as a 12-bit binary digital code. It contains a main sensor, remote probes and an Analog-to-Digital...
207
200.0
Post-Quantum Cryptography - xQlave® PQC ML-KEM (Kyber)
In a world where advances in quantum computing threaten traditional cryptographic systems, Xiphera’s xQlave® ML-KEM (Kyber) Key Encapsulation Mechanis...
208
130.0
LPDDR6, LPDDR5X Combo PHY & Controller
INNOSILICON™ introduces its LPDDR6/5X PHY and Controller IP, purpose-built for the AI era’s high-performance chip design needs. This solution is fully...
209
105.0
CME IoT platform
Sensor-Mate (sensing node)Long distance wireless communication (920MHz)Sensor-Gateway (Aggregator)920MHz wireless module (CM Engineering proprietary)G...
210
100.0
MACsec - Extreme-speed - Security Protocol
MACsec is a point-to-point protocol located on layer two (Data Link) of the OSI model. Xiphera's comprehensive MACsec solution portfolio safeguards th...
211
100.0
PCIe 5.0 PHY & Controller
The Innosilicon Gen1/2/3/4/5 PCI Express Controller provides a PCI Express Root Complex (RC) and Endpoint (EP) application. It’s a high performance, h...
212
100.0
Post-Quantum Cryptography - nQrux® Quantum Secure Boot
nQrux® Quantum Secure Boot enhances system security by enabling quantum-secure authenticated boot, crucial for verifying the authenticity and integrit...
213
100.0
Post-Quantum Cryptography - xQlave® PQC ML-DSA (Dilithium)
The xQlave® ML-DSA (Dilithium) Digital Signature Algorithm IP core secures critical infrastructures and operations against the threat of quantum compu...
214
100.0
LPDDR5X, LPDDR5, LPDDR4X, LPDDR4 Combo PHY & Controller
The INNOSILICON™ LPDDR IP includes a LPDDR5X/5/4X/4 Combo PHY and controller. It is fully compliant with the JEDEC standard. Optimized for low-power a...
215
80.0
GDDR7 PHY & Controller
The INNOSILICON™ GDDR7 PHY is fully compliant with the JEDEC GDDR7 standard, supporting data rates of up to 32 Gbps in PAM3 mode. In PAM3 mode, each b...
216
60.0
UCIe Chiplet PHY & Controller
INNOSILICON™ UCIe Chiplet IP offers a customizable solution for seamless, low-latency data transfer between silicon dies and chips, enabling heterogen...
217
51.0
TLS 1.3 - Security Protocol
Transport Layer Security (TLS) is a cryptographic protocol used for building a secure connection between a client and a server over the Internet. A ha...
218
51.0
True Random Number Generator (TRNG)
The TRNG IP core establishes a benchmark for hardware-based security in cryptographic systems, by generating high-entropy, true random numbers essenti...
219
50.0
AES - GCM - Extreme-speed variant
XIP1113E is a an extreme-speed IP core implementing the Advanced Encryption Standard (AES) in Galois Counter Mode (GCM). AES-GCM is a widely used cryp...
220
50.0
IPsec - Security Protocol
IPsec (Internet Protocol Security) is a widely implemented protocol to secure communications across the Internet. Xiphera’s IPsec core enhances secure...
221
48.0
nQrux® Crypto Module
Xiphera’s nQrux® Crypto Module IP core provides a comprehensive security platform that allows for customisation of top-notch cryptographic services, s...
222
43.0
Elliptic Curve Cryptography (ECC) Accelerator
The high-speed ECC Accelerator reaches to more than a thousand operations per second in a modern FPGA or ASIC. Furthermore, it covers all NIST P curve...
223
25.0
HBM4, HBM3E PHY & Controller
INNOSILICON™ HBM4/3E IP is fully compliant with the JEDEC standard for HBM3E and the preliminary specification for HBM4. The IP includes a customizabl...
224
25.0
DDR5, DDR4 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal DDR5/4 Combo PHY s provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDR...
225
15.0
GDDR6X, GDDR6 Combo PHY & Controller
The INNOSILICON™ GDDR6X/6 PHY is fully compliant with the JEDEC GDDR6X/6 standard, supporting data rates of up to 20 Gbps per pin for PAM2 GDDR6 mode ...
226
3.0
Pseudorandom Number Generator (PRNG) - Balanced variant
The PRNG IP core establishes a benchmark for hardware-based security in cryptographic systems by generating high-quality pseudorandom numbers. It deli...
227
3.0
Pseudorandom Number Generator (PRNG) - High-speed variant
The PRNG IP core establishes a benchmark for hardware-based security in cryptographic systems by generating high-quality pseudorandom numbers. It deli...
228
2.0
HBM3, HBM3E PHY & Controller
This document describes a general layout scheme and Innosilicon HBM3/3E PHY connecting to the controller using a DFI digital interface. All interface ...
229
2.0
Innosilicon - High-Quality ASIC Customization Services
With a team of first-class experts, highly-reliable chip customization ability, and rich experience in mass production on processes from 55nm to 5nm, ...
230
1.0
10G Multi-SerDes PHY
The Innosilicon 10G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 10Gbps within a single lane. The PHY can be configured ...
231
1.0
12.5G Multi-SerDes PHY
The Innosilicon 12.5G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 12.5Gbps within a single lane. For this particular da...
232
1.0
32G Multi-SerDes For PCIe5.0/USB3.x PHY
The Innosilicon 32G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 32Gbps within a single lane. For this datasheet, the PH...
233
1.0
32G Multi-SerDes PHY + Controller
The INNOSILICON™ 32G Multi-SerDes PHY is a highly configurable IP solution capable of supporting data rates of up to 32 Gbps per lane. It is designed ...
234
1.0
64G/56G SerDes
The Innosilicon 64G/56G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 56Gbps within a single lane. For this datasheet, th...
235
1.0
25G Multi-SerDes PHY
The Innosilicon 25G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 25Gbps within a single lane. For this particular datash...
236
1.0
HBM2E PHY&Controller
Innosilicon HBM2E PHY IP is a silicon proven product with max speed up to 3600Mbps per DQ data, HBM2E memory has 1024bit DQ, total bandwidth can be 3....
237
1.0
HBM2E/2 Combo PHY&Controller
Innosilicon HBM2E/2 Combo PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible HBM devices. It is optimized ...
238
1.0
HBM3/2E Combo PHY&Controller
The third-generation HBM (HBM3/2E) technology, outlined by the JESD235C standard, inherits physical 128-bit DDR interface with 2n/4n prefetch architec...
239
1.0
PCIe 4.0 Controller
The Innosilicon Gen1/2/3/4 PCI Express Controller provides a PCI Express Root Complex (RC) and Endpoint (EP) application. It’s a high performance, hig...
240
1.0
PCIe 4.0 PHY
The Innosilicon PCIe4.0 PHY is a highly configurable PHY capable of supporting speeds up to 16Gbps within a single lane. For this particular datasheet...
241
1.0
PCIe 6.0, CXL3.0 PHY & Controller
INNOSILICON™ PCIe 6.0 and CXL 3.0 IP solutions combines a high-performance controller and PHY and is fully compliant with PCIe 6.0, CXL 3.0, and PIPE ...
242
1.0
MCR DDR5 PHY
The INNOSILICON DDR Mixed-Signal MCR DDR5 PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible MCR DDR5 DIMM...
243
1.0
HDMI1.4 Receiver PHY
Innosilicon HDMI RX IP is designed to receive and recover the video and audio data from an HDMI source device for display applications. Innosilicon H...
244
1.0
HDMI1.4 Transmitter IP
Innosilicon HDMI TX IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with HDMI...
245
1.0
HDMI2.0 Receiver PHY
Innosilicon HDMI RX IP is designed to receive and recover the video and audio data from an HDMI source device for display applications. Innosilicon H...
246
1.0
HDMI2.0 Receiver PHY & Controller
Innosilicon HDMI RX IP is composed of the digital controller, the PHY logic and physical layer. The digital controller receives video, audio, synchron...
247
1.0
HDMI2.0 TX Controller
Innosilicon HDMI TX Controller is designed for transmitting video and audio data from a video source device to a display device, which is compatible w...
248
1.0
HDMI2.0 TX PHY
Innosilicon HDMI TX IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with HDMI...
249
1.0
HDMI2.0/1.4 RX PHY & Controller
Innosilicon HDMI RX IP is designed to receive and recover the video and audio data from a HDMI source device for display applications, which is compat...
250
1.0
HDMI2.0/1.4 TX PHY & Controller
Innosilicon HDMI TX IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with HDMI...