Design & Reuse
4907 IP
4751
0.0
Signle Port High-Current SRAM Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option
Signle Port High-Current SRAM Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option...
4752
0.0
Signle Port High-Density SRAM Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option
Signle Port High-Density SRAM Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option...
4753
0.0
Signle Port Multi-Bank High-Density SRAM Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option
Signle Port Multi-Bank High-Density SRAM Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT...
4754
0.0
Silicon Security Solution
ChevinID™ was designed by Chevin Technology using patented method (GB2609026) to add a further layer of protection to your Silicon supply chain by ide...
4755
0.0
Silicon Storage Technology - Custom Design Services
Silicon Storage Technology, Inc. (SST), is the creator of SuperFlash® , an innovative, highly reliable and versatile type of NOR Flash memory. SST, th...
4756
0.0
Single Port SRAM Compiler IP, 4.0um2 bit cells, Synchronous high density, UMC 0.18um HV process
UMC 0.18um high voltage 1.8V process synchronous high density Single Port SRAM memory compiler....
4757
0.0
mioty - The Wireless IoT Technology
Wireless data transmission systems are being increasingly deployed in industrial and home automation applications. These robust systems are used to tr...
4758
0.0
MIPI C-PHY DSI RX IP
Innosilicon MIPI DSI RX IP implements the MIPI C-PHY as well as MIPI DSI protocols. The DSI link protocol specification is a part of group of communic...
4759
0.0
MIPI C-PHY DSI TX IP
Innosilicon MIPI DSI Transmitter implements the DSI protocol as well as MIPI C-PHY protocol. The DSI link protocol specification is a part of group of...
4760
0.0
MIPI C-PHY RX PHY
The Innosilicon MIPI C-PHY provides a C-PHY in a single IP core, which integrates a compatible PHY that supports high speed data receiver, plus a MIPI...
4761
0.0
MIPI C-PHY TX PHY
The Innosilicon MIPI C-PHY provides a C-PHY in a single IP core, which integrates a compatible PHY that supports high speed data receiver, plus a MIPI...
4762
0.0
MIPI C/D-PHY CSI-2 RX IP
Innosilicon CSI-2 Receiver implements MIPI CSI-2 as well as C/D-PHY protocols. The CSI-2 link protocol specification is a part of group of communicati...
4763
0.0
MIPI C/D-PHY RX
The Innosilicon MIPI C/D-PHY RX provides D-PHY and C-PHY in a single IP core. It integrates a compatible PHY that supports high speed data receiver, p...
4764
0.0
MIPI C/D-PHY TX
The Innosilicon MIPI C/D PHY TX integrates a MIPI C-PHY and a MIPI D-PHY in a single IP core, which provides a MIPI high speed data plus low-power low...
4765
0.0
MIPI CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
4766
0.0
MIPI CSI-2 TX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
4767
0.0
MIPI D-PHY Combo LVDS CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2, MIPI D-PHY, and LVDS protocols. The CSI-2 link protocol specification is a part of group of communication...
4768
0.0
MIPI D-PHY Combo LVDS DSI TX IP
Innosilicon MIPI DSI Transmitter implements DSI, MIPI D-PHY, and LVDS protocol. The DSI link protocol specification is a part of group of communicatio...
4769
0.0
MIPI D-PHY CSI-2 RX IP
Innosilicon CSI-2 Receiver implements MIPI CSI-2 protocol as well as D-PHY protocol. The CSI-2 link protocol specification is a part of group of commu...
4770
0.0
MIPI D-PHY DSI 1.2G RX IP
Innosilicon MIPI DSI receiver implements the MIPI DSI as well as D-PHY protocols. The DSI link protocol specification is a part of group of communicat...
4771
0.0
MIPI D-PHY DSI 1.5G RX IP
Innosilicon MIPI DSI RX IP implements the MIPI D-PHY as well as MIPI DSI protocols. The DSI link protocol specification is a part of group of communic...
4772
0.0
MIPI D-PHY DSI TX IP
Innosilicon MIPI DSI Transmitter implements the DSI protocol as well as MIPI D-PHY protocol. The DSI link protocol specification is a part of group of...
4773
0.0
MIPI D-PHY RX/TX v1.1 / v1.2 IP in TSMC (12/16nm, 28nm, 40nm, and 55nm process)
The D-PHY is a popular MIPI physical layer developed for mobile applications because it is a flexible, high-speed, low-power and low-cost solution. As...
4774
0.0
MIPI D-PHY TX
The Innosilicon MIPI D-PHY TX provides a MIPI® high speed data plus low-power low speed transmitter that supports data transfer in the bi-directional ...
4775
0.0
MIPI D-PHY TX COMBO LVDS PHY
The Innosilicon MIPI D-PHY TX combo LVDS PHY integrates a D-PHY and a LVDS in a single IP core, which provides a MIPI® high speed data plus low-power ...
4776
0.0
MIPI D-PHY TX Combo TTL PHY
The Innosilicon MIPI D-PHY TX provides a MIPI® high speed data plus low-power low speed transmitter that supports data transfer in the bi-directional ...
4777
0.0
MIPI D-PHY_1.2G CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
4778
0.0
MIPI D-PHY_1.5G CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
4779
0.0
MIPI D-PHY_2.5G CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
4780
0.0
MIPI D-PHY_4.5G CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
4781
0.0
MIPI DPHY DSI TX IP
Innosilicon MIPI DSI Transmitter implements the DSI protocol as well as MIPI D-PHY protocol. The DSI link protocol specification is a part of group of...
4782
0.0
MIPI DPHY1.2 RX (support combo TTL, LVDS, HiSPI)
The Innosilicon MIPI D-PHY IP provides D-PHY in a single IP core. It integrates a compatible PHY that supports high speed data receiver, plus a MIPI® ...
4783
0.0
MIPI DPHY2.0/CPHY1.1 TX (support combo TTL, LVDS, HiSPI)
The Innosilicon MIPI C/D PHY TX integrates a MIPI C-PHY and a MIPI D-PHY in a single IP core, which provides a MIPI high speed data plus low-power low...
4784
0.0
MIPI DSI-2 DSC RX IP
Innosilicon MIPI DSI-2 DSC RX IP implements the MIPI C/D-PHY as well as MIPI DSI-2 protocols and contains the DSC (Display Stream Compression) algorit...
4785
0.0
MIPI M-PHY
INNOSILICON™ M-PHY IP implements the MIPI M-PHY protocol V4.1. The M-PHY protocol specification is a part of a group of communication protocols define...
4786
0.0
Circuit Camouflage Technology
Rambus Circuit Camouflage Technology (formerly Inside Secure), also known as SecureMedia Library (SML), is an anti-reverse engineering and anti-clonin...
4787
0.0
VIS 150nm 5V Bandgap voltage reference
The OT0118 is a medium precision, bandgap voltage reference and current reference generator specifically tuned for the VIS 150nm CMOS process....
4788
0.0
BLE 5.2 RF IP (RFIP) in SMIC55
Low cost and high-performance BLE5.2 RF-IP overall solution...
4789
0.0
BLE 5.2/BT 5.0 Dual Mode RF IP (RFIP) in SMIC55
Low cost and high-performance BLE/BT dual-mode RF-IP overall solution...
4790
0.0
PLL
INNOSILICON™ PLL IP is a high-speed, low-jitter frequency synthesizer, developed to reduce time-to-market, risk, and design cost. It can generate a st...
4791
0.0
DLL
The INNOSILICON™ Delay-Locked Loop (DLL) PHY is a mix-signal circuit used in low-power and high-speed applications to align and synchronize clock sign...
4792
0.0
Floating point adder
Floating point adder...
4793
0.0
Floating point MAC
Floating point MAC...
4794
0.0
Floating point multiplier
Floating point multiplier...
4795
0.0
Ultra High Density, 5-track, 3nm channel length, 48nm poly pitch TSMC 2nm Plus
Ultra High Density, 5-track, 3nm channel length, 48nm poly pitch TSMC 2nm Plus...
4796
0.0
Ultra High Density, 6-track, 3nm channel length, 48nm poly pitch TSMC 2nm Plus
Ultra High Density, 6-track, 3nm channel length, 48nm poly pitch TSMC 2nm Plus...
4797
0.0
Ultra-low power consumption out-of-order commercial-grade 64-bit RISC-V CPU IP
StarFive Dubhe-70 is a 9+ stage, 3-issue, out-of-order CPU IP that supports the rich RISC-V instruction set, RV64GCBH_Zicond_Zicbom_Zicboz_Zicbop.With...
4798
0.0
HMAC-SHA256 Accelerator
Chevin Technology’s HMAC-SHA256 cryptographic accelerator function is used to securely generate and verify message authentication codes. Message authe...
4799
0.0
UMC 130nm Bandgap
The OT0118 is a medium precision, bandgap voltage reference and current reference generator specifically tuned for the UMC 130nm CMOS process....
4800
0.0
CMC Microsystems - technology research support
CMC helps researchers and industry across Canada's National Design Network® develop innovations in microsystems and nanotechnologies. The scope of se...