1751 1.0

USB 3.0 SSIC PHY The Arasan Superspeed Inter-chip Controller (USB 3.0 SSIC Adapter) uses Arasan’s MIPI-M-PHY (Type-1) v. 3.0 to implement the SSIC adaptation to the US...

1752 1.0

USB HSIC PHY - High Speed Inter-Chip IP Core USB is the ubiquitous peripherals interconnect of choice for large number of computing and consumer applications. Many systems provide a comprehensive...

1753 1.0

TSMC CL013G 130nm Clock Generator PLL - 136MHz-680MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1754 1.0

TSMC CL013G 130nm Clock Generator PLL - 272MHz-1360MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1755 1.0

TSMC CL013G 130nm Clock Generator PLL - 68MHz-340MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1756 1.0

TSMC CL013G 130nm DDR DLL - 107MHz-535MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1757 1.0

TSMC CL013G 130nm DDR DLL - 51MHz-255MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1758 1.0

TSMC CL013G 130nm DDR DLL - 68MHz-340MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1759 1.0

TSMC CL013G 130nm Deskew PLL - 136MHz-680MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1760 1.0

TSMC CL013G 130nm Deskew PLL - 272MHz-1360MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1761 1.0

TSMC CL013G 130nm Deskew PLL - 68MHz-340MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1762 1.0

TSMC CL013G 130nm General Purpose PLL - 136MHz-680MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

1763 1.0

TSMC CL013G 130nm Spread Spectrum PLL - 136MHz-680MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1764 1.0

TSMC CL013G 130nm Spread Spectrum PLL - 272MHz-1360MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1765 1.0

TSMC CL013G 130nm Spread Spectrum PLL - 68MHz-340MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1766 1.0

TSMC CL013LP 130nm Clock Generator PLL - 110MHz-550MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1767 1.0

TSMC CL013LP 130nm Clock Generator PLL - 220MHz-1100MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1768 1.0

TSMC CL013LP 130nm Clock Generator PLL - 55MHz-275MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1769 1.0

TSMC CL013LP 130nm DDR DLL - 42MHz-210MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1770 1.0

TSMC CL013LP 130nm DDR DLL - 56MHz-280MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1771 1.0

TSMC CL013LP 130nm DDR DLL - 88MHz-440MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1772 1.0

TSMC CL013LP 130nm Deskew PLL - 110MHz-550MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1773 1.0

TSMC CL013LP 130nm Deskew PLL - 220MHz-1100MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1774 1.0

TSMC CL013LP 130nm Deskew PLL - 55MHz-275MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1775 1.0

TSMC CL013LP 130nm General Purpose PLL - 110MHz-550MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

1776 1.0

TSMC CL013LP 130nm Spread Spectrum PLL - 110MHz-550MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1777 1.0

TSMC CL013LP 130nm Spread Spectrum PLL - 220MHz-1100MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1778 1.0

TSMC CL013LP 130nm Spread Spectrum PLL - 55MHz-275MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1779 1.0

TSMC CL013LV 130nm Clock Generator PLL - 160MHz-800MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1780 1.0

TSMC CL013LV 130nm Clock Generator PLL - 320MHz-1600MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1781 1.0

TSMC CL013LV 130nm Clock Generator PLL - 80MHz-400MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1782 1.0

TSMC CL013LV 130nm DDR DLL - 139MHz-695MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1783 1.0

TSMC CL013LV 130nm DDR DLL - 66MHz-330MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1784 1.0

TSMC CL013LV 130nm DDR DLL - 88MHz-440MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1785 1.0

TSMC CL013LV 130nm Deskew PLL - 160MHz-800MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1786 1.0

TSMC CL013LV 130nm Deskew PLL - 320MHz-1600MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1787 1.0

TSMC CL013LV 130nm Deskew PLL - 80MHz-400MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1788 1.0

TSMC CL013LV 130nm General Purpose PLL - 160MHz-800MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

1789 1.0

TSMC CL013LV 130nm Spread Spectrum PLL - 160MHz-800MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1790 1.0

TSMC CL013LV 130nm Spread Spectrum PLL - 320MHz-1600MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1791 1.0

TSMC CL013LV 130nm Spread Spectrum PLL - 80MHz-400MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1792 1.0

TSMC CL013LVOD 130nm Clock Generator PLL - 110MHz-550MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1793 1.0

TSMC CL013LVOD 130nm Clock Generator PLL - 220MHz-1100MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1794 1.0

TSMC CL013LVOD 130nm Clock Generator PLL - 440MHz-2200MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1795 1.0

TSMC CL013LVOD 130nm DDR DLL - 116MHz-580MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1796 1.0

TSMC CL013LVOD 130nm DDR DLL - 183MHz-915MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1797 1.0

TSMC CL013LVOD 130nm DDR DLL - 87MHz-435MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1798 1.0

TSMC CL013LVOD 130nm Deskew PLL - 110MHz-550MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1799 1.0

TSMC CL013LVOD 130nm Deskew PLL - 220MHz-1100MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1800 1.0

TSMC CL013LVOD 130nm Deskew PLL - 440MHz-2200MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...