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HBM3 PHY on TSMC N3P The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...

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VC Functional Safety Manager VC Functional Safety Manager provides a comprehensive tool for IP and semiconductor groups targeting functional safety certification for ISO 26262, IE...

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VC Verification IP for AMBA 4 AXI Synopsys VC Verification IP (VIP) for ARM® AMBA® AXI™ provides complete protocol support for AXI3™, AXI4™, AXI4-Lite™, AXI4-Stream™, ACE™, ACE-Lite™ ,...

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VC Verification IP for AMBA 5 CHI Synopsys VC Verification IP (VIP) for ARM® AMBA® 5 CHI protocol specification provides a comprehensive set of protocol, methodology, verification and ...

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VC Verification IP for CPRI Synopsys® VC Verification IP for CPRI provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users t...

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VC Verification IP for DDR5 Synopsys® VC Verification IP for JEDEC DDR5, deployed in November 2016, provides a comprehensive set of protocol, methodology, verification, and produ...

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VC Verification IP for Ethernet ...

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VC Verification IP for Ethernet Synopsys VC Verification IP (VIP) for Ethernet provides complete support for Ethernet 10/100/1000M/10G/40G and 100G interfaces. With a comprehensive s...

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VC Verification IP for Fibre Channel Synopsys VC Verification IP (VIP) for Fibre Channel is designed to thoroughly verify Fibre Channel designs using both random and directed simulation. ...

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VC Verification IP for HDMI Synopsys VC Verification IP (VIP) for HDMI provides a comprehensive set of protocol, methodology, verification and productivity features, enabling use...

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VC Verification IP for HSI Synopsys VC Verification IP for MIPI HSI is a comprehensive VIP solution enabling pre-silicon functional verification of MIPI HSI (High-speed synchron...

2412 0.0

VC Verification IP for I2C Synopsys VC Verification IP for I2C includes all protocol speeds. With a comprehensive set of protocols, methodology, verification and ease-of-use fea...

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VC Verification IP for I2S Synopsys VC Verification IP (VIP) for I2S provides a comprehensive set of protocol, methodology, verification and productivity features, enabling user...

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VC Verification IP for Interlaken Synopsys® VC Verification IP for Interlaken provides a comprehensive set of protocol, methodology, verification and productivity features, enabling us...

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VC Verification IP for MIPI CSI-2 (C-PHY / D-PHY) Synopsys VC Verification IP (VIP) for MIPI Camera Serial Interface 2 (CSI-2) provides a comprehensive set of protocol, methodology, verification and p...

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VC Verification IP for MIPI DigRFv4 Synopsys VC Verification IP for MIPI DigRF provides a comprehensive set of protocol, methodology, verification and productivity features, enabling use...

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VC Verification IP for MIPI DSI Synopsys VC Verification IP for MIPI Display Serial Interface (DSI) provides a comprehensive set of protocol, methodology, verification and productivi...

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VC Verification IP for MIPI DSI Synopsys® Verification IP (VIP) for UCIe provides a comprehensive set of protocol, multi-die, methodology, verification, and productivity features ena...

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VC Verification IP for MIPI M-PHY Synopsys VC Verification IP for MIPI M-PHY provides a comprehensive set of protocol, methodology, verification and productivity features, enabling use...

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VC Verification IP for NVMe Synopsys VC VIP for Non-Volatile Memory Express (NVMe) is designed to help thoroughly verify NVMe designs using both random and directed simulation....

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VC Verification IP for OCP Synopsys VC Verification IP (VIP) for OCP provides a comprehensive set of protocol, methodology, verification and productivity features enabling users...

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VC Verification IP for PCIe Synopsys VC Verification IP (VIP) for PCI Express (PCIe) provides a comprehensive set of protocol, methodology, verification and productivity features...

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VC Verification IP for SAS Synopsys VC Verification IP (VIP) Serial SCSI (SAS) is designed to thoroughly verify your design using both random and directed simulation....

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VC Verification IP for SATA Synopsys VC Verification IP (VIP) for Serial ATA (SATA) is designed to verify SATA-based designs using both random and directed simulation....

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VC Verification IP for SDIO Synopsys VC Verification IP (VIP) for SDIO is a comprehensive VIP solution enabling pre-silicon functional verification of SD (Secure Digital) IO/Memo...

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VC Verification IP for TileLink Synopsys® Verification IP for TileLink provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users ...

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VC Verification IP for UART Synopsys VC Verification IP (VIP) for UART provides a comprehensive set of protocol, methodology, verification and productivity features, enabling use...

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VC Verification IP for UFS Synopsys® VC Verification IP for the JEDEC UFS memory protocol specification provides a comprehensive set of protocol, methodology, verification and p...

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VC Verification IP for USB Synopsys® VC Verification IP for USB provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to ...

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TCAM Compilers for Samsung (14nm, 10nm, SF5A, SF4X) Synopsys embedded ternary content addressable memories (TCAMs) help networking designers meet the demand for wire-speed packet processing, access cont...

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TCAM Compilers for SMIC (28nm) Synopsys embedded ternary content addressable memories (TCAMs) help networking designers meet the demand for wire-speed packet processing, access cont...

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TCAM Compilers for TSMC (65nm, 40nm, 28nm, 16nm, N7, N6, N5, N4 Synopsys embedded ternary content addressable memories (TCAMs) help networking designers meet the demand for wire-speed packet processing, access cont...

2433 0.0

Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers The Digital Blocks DB-DMAC-MC-AXI4-MM-STREAM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Mem...

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Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers The Digital Blocks DB-DMAC-MC-AXI4-MM-STREAM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Mem...

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ECC Core Rambus Error Correction Coding (ECC) Core implements the standard Hamming Code based DRAM Single Error Correction (SEC) and Double Error Detection (DE...

2436 0.0

ACCUREF - Low Power Voltage and Current Reference Circuit, 0.3% Accuracy, 90 dB PSR in TSMC C130BCD This intellectual property (IP) core generates a precise/adjustable reference voltage (VREF), as well as two sets of reference output currents using b...

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LCD Controller - TFT LCD Panels (AXI4 Bus) The Digital Blocks DB9000AXI4 TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 4.0 AXI4 Protocol Interconne...

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PCI Express (PCIe) 6.0 Controller Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 6.0 provides the logic required to integrate a roo...

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PCI Express (PCIe) 7.0 Controller Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 7.0 provides the logic required to integrate a roo...

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PCI Express Verification Component The PCI Express eVC can be used for verification of a device that supports the PCI Express standard. The eVC is compliant to PCI Express Base Specific...

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PCI Master/Target Interface Core ...

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PCI to AMBA AHB Host Bridge This PCI Host Bridge IP core enables data transfers between an AMBA® AHB host processor bus system and PCI bus based devices. The bridge enables high...

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PCI-X Arbiter Supporting 66 / 100 / 133MHz In PCI-X systems, a central controller is used to manage bus ownership. This controller, called arbiter, selects the next master during The PCIXarbit...

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PCI-X Verification Component eVCs are reusable Verification Components that can be used to establish ready-made verification environment. Each eVC is capable of acting as full ver...

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PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect Rambus PCIe 1.1 Controller with AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 1.1 ...

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PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect Rambus PCIe 2.1 Controller with AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 2.1 ...

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PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support Rambus PCIe 2.1 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 2.1 Controlle...

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PCIe 3.0 PHY in Samsung (SF5A The multi-channel Synopsys PHY IP for PCI Express® 3.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...

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PCIe 3.0 PHY in TSMC (28nm, 12nm, N4P) The multi-channel Synopsys PHY IP for PCI Express® 3.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...

2450 0.0

PCIe 3.0, 2.1, 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with AMBA AXI User Interface Rambus PCIe 3.0 with AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 3.0 with AXI is...