Design & Reuse
4791 IP
251
30.0
WAVE-N, Specialized video processing NPU for SR, NR, Demosaic New!
Chips&Media's WAVE-N is the high-performance application-specific, neural processor IP for edge devices. WAVE-N is based on efficient hardware archi...
252
30.0
Media Access Control Security (MACSec)
Media Access Control Security (MACSec) is an IEEE standards-based protocol for securing communication among the trusted components of an 802.1 LAN. MA...
253
30.0
Deeply Embedded AI Accelerator for Microcontrollers and End-Point IoT Devices
The NeuroMosaic Processor (NMP) family is shattering the barriers to deploying ML by delivering a general-purpose architecture and simple programmer’s...
254
30.0
Temperature Sensor with Digital Output (High accuracy thermal sensing for reliability and optimisation), TSMC N7
A high precision low power junction temperature sensor that has been developed to be easily embedded into digital ASIC designs. The block features an ...
255
30.0
Performance Efficiency Leading AI Accelerator for Mobile and Edge Devices
The NeuroMosaic Processor (NMP) family is shattering the barriers to deploying ML by delivering a general-purpose architecture and simple programmer’s...
256
30.0
Ceva-MotionEngine™
Ceva-MotionEngine is Ceva’s core sensor processing software system and is the product of over 20 years of experience developing sensor-based technolog...
257
30.0
Thermal Diode (TD) with Base Pin, TSMC N7
Thermal diodes provide a useful means for monitoring junction temperature on die and are typically independently powered from the rest of the SoC. The...
258
30.0
Thermal Diode for fast and coarse temeprature measurement
Thermal diodes provide a useful means for monitoring junction temperature on die and are typically independently powered from the rest of the SoC. The...
259
30.0
Thermal Diode for fast and coarse temeprature measurement
Thermal diodes provide a useful means for monitoring junction temperature on die and are typically independently powered from the rest of the SoC. The...
260
30.0
Thermal Diode for fast and coarse temperature measurement
Thermal diodes provide a useful means for monitoring junction temperature on die and are typically independently powered from the rest of the SoC. The...
261
30.0
High-efficiency vector DSP cores for 5G and 5G-Advanced
The Ceva-XC21 is the most efficient vector DSP core available today for communications applications. The Ceva-XC21 DSP is designed for low-power, cos...
262
30.0
High-Performance Edge AI Accelerator
The NeuroMosaic Processor (NMP) family is shattering the barriers to deploying ML by delivering a general-purpose architecture and simple programmer’s...
263
30.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPM-NS
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
264
30.0
Universal Chiplet Interconnect Express (UCIe) Controller
Integrating multiple chiplets within a single package has become crucial for high-performance computing. CoMira’s UCIe (Universal Chiplet Interconnect...
265
30.0
Voltage Monitor with Digital Output, TSMC N7
The voltage monitor is a low power self-contained IP block specially designed to monitor voltage levels within the core logic voltage domains and prov...
266
30.0
Low-power, high-speed 11-bit 4GSPS SAR (ADC) TSMC 28nm HPC+
The A11B4G is a low-power, high-speed analog to digital converter (ADC) intellectual property (IP) design block. It is a hybrid successive approximati...
267
30.0
Low-power, high-speed 11-bit, 8 GSPS Analog to Digital Converter (ADC) IP block TSMC 28nm HPC+ process
The A11B8G is a low-power, high-speed analog to digital converter (ADC) intellectual property (IP) design block. It is a hybrid successive approximati...
268
30.0
Process Detector (For DVFS and monitoring process variation), TSMC N7
An embedded process detector circuit which helps Integrated Circuit (IC) developers to address the problem of process variability on low-geometry CMOS...
269
30.0
TSMC CLN7FF 7nm Deskew PLL - 400MHz-2000MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
270
30.0
TSMC CLN7FF 7nm General Purpose PLL - 400MHz-2000MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
271
30.0
TSMC CLN7FF 7nm IoT PLL - 30MHz-1000MHz
The IoT PLL is designed for very low power, sipping only 45uW at 30MHz and running from core power. It has a wide frequency range with multiplication ...
272
30.0
TSMC CLN7FF 7nm Multi Phase DLL - 800MHz-4000MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
273
30.0
Multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC)
CoMira’s multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC) is fully configurable and pro...
274
28.0
Display Controller - LCD / OLED Panels (AXI Bus)
The Digital Blocks DB9000AXI LCD / OLED Display Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI Protocol Inter...
275
28.0
Display Controller - LCD / OLED Panels (AXI4 Bus)
The Digital Blocks DB9000AXI4 LCD / OLED Display Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI4 Protocol Int...
276
28.0
Slave side SPI/QPI controller 133MHZ
This SPI/QPI PHY IP is fully compatible with Macronix NOR Flash SPI products. Max frequency hardware proven is 133MHz. Can be used for a variety of m...
277
28.0
LPDDR4x Secondary/Slave (memory side!) PHY
This LPDDR4X PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR4X IP pr...
278
28.0
LPDDR4x/5 Secondary/Slave (memory side!) PHY
This LPDDR4/4X/5 PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR4X/L...
279
28.0
LPDDR5 Secondary/Slave (memory side!) PHY
This LPDDR5 PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR5 IP prov...
280
28.0
LPDDR5X Secondary/Slave (memory side!) PHY
This LPDDR5X PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR5X IP pr...
281
25.0
I3C Advanced Controller, V1.1
I3C is a new a standard from the MIPI Alliance that unifies and extends the legacy interfaces of I2C and SPI and adds new powerful features to sup...
282
25.0
I3C Advanced Controller, V1.1 Lite
The I3C Advanced Controller Lite is a highly configurable I3C controller that can be used in microcontroller-based environments to provide I3C con...
283
25.0
I3C Advanced Target, V 1.1 Lite
The I3C Advanced Target Lite is a highly configurable I3C Target that can be used in microcontroller based environments to provide I3C connectivit...
284
25.0
I3C Advanced Target, V1.1
The I3C Advanced Target is a highly configurable I3C Target that can be used in microcontroller based environments to provide I3C connectivity to ...
285
25.0
I3C Autonomous Target, V1.1
The I3C Autonomous Target is intended for simple, data acquisition types of applications where a microprocessor is not needed to process the data....
286
25.0
WAVE-P, Advanced Professional Video, APV New!
Advanced Professional Video (APV) codec is a new codec for prosumers ​ who do not want to compromise on quality while enjoying the convenience of ​ ...
287
25.0
HBM2E PHY V2 (Hard 1) in TSMC (N7, N6, N5)
The Synopsys HBM2/HBM2E PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), graphics, and networking A...
288
25.0
HBM2E PHY V2 in TSMC (N7, N6, N5)
The Synopsys HBM2/HBM2E PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), graphics, and networking A...
289
25.0
LDO Voltage Regulator 250 mA, TSMC N3P
The LDO IP is a 1.2V low-quiescent-current adjustable output voltage Low-Drop-Out (LDO) Linear Regulator implemented in the TSMC 3nm N3P CMOS process ...
290
25.0
LDO Voltage Regulator Adjustable 0.45 V to 0.9 V Output, 30 mA
The LDO IP is a 1.2V low-quiescent-current adjustable output voltage Low-Drop-Out (LDO) Linear Regulator implemented in the TSMC 3nm N3P CMOS process ...
291
25.0
1G/10G TCP/IP Hardware Stack
The TCPIP-1G/10G core implements a complete TCP/IP Hardware Protocol Stack. More capable than many offloading engines, it allows systems to connect to...
292
25.0
LINFlexD Controller
The LINFlexD Controller is a serial communication interface designed for Local Interconnect Network (LIN) applications. The LINFlexD manages a high nu...
293
25.0
MIPI C-PHY v1.1
Combination MIPI CPHY-DPHY Analog Interface The MIPI C-PHY V1.0 improves throughput over a bandwidth limited channel, allowing more data without in...
294
25.0
MIPI C-PHY V1.1 TSMC 28nm HPC+
Combination MIPI CPHY-DPHY Analog Interface The MIPI C-PHY V1.1 improves throughput over a bandwidth limited channel, allowing more data without in...
295
25.0
MIPI C-PHY-D-PHY Combo PHY IP on TSMC 28nm HPC+
Combination MIPI CPHY-DPHY Analog Interface The MIPI C-PHY V1.0 improves throughput over a bandwidth limited channel, allowing more data without in...
296
25.0
MIPI D-PHY Tx v1.1 ONLY @1.5ghz Ultra Low Power & Low Area for IoT & Wearables
Arasan 2nd Generation MIPI D-PHY v1.1 IP supporting speeds of up to 1.5 Gbps on TSMC 22nm process technology for SoC designs. Arasan’s D-PHY IP is a...
297
25.0
MIPI D-PHY V1.2@2.5GHz TSMC28nm HPC+
Arasan has the industry’s broadest portfolio of foundry and process technology support for MIPI D-PHY in the industry. The MIPI D-PHY analog IP is ava...
298
25.0
FlexCAN Controller
The FlexCAN controller is a highly configurable, synthesizable core implementing the CAN protocol (ISO 11898-1), CAN with Flexible Data rate (CAN FD),...
299
25.0
FlexRay Controller
The FlexRay Controller fully complies with FlexRay Communication System Protocol Specification, Version 2.1, Revision A. It implements the specificati...
300
25.0
Ultra-Fast Baseline and Extended JPEG Decoder Core
This JPEG decompression IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements ...