401 20.0

IO 1.8V LVDS Automotive Grade 1 GF (22nm) Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...

402 20.0

IO 1.8V LVDS in GF (22nm) Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...

403 20.0

IO 1.8V LVDS Rx in GF (12nm) Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...

404 20.0

IO 3.3V eMMC in GF (22nm) Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...

405 20.0

IO 3.3V LVDS Rx Automotive Grade 2 in GF (12nm) Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...

406 20.0

IO 3.3V LVDS Rx in GF (12nm) Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...

407 20.0

IO GPIO in TSMC for Automotive Grade 1 (22nm) Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

408 20.0

IO I2C 3.3V in GF (22nm) Synopsys Inter-Integrated Circuit (I2C) I/O library is used for two wire interfaces to connect low-speed devices like EEPROM, A/D, and D/A converters ...

409 20.0

IO I3C 3.3V in GF (22nm) Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...

410 20.0

IP Prototyping Kits for USB, DDR, MIPI, PCI Express protocols The Synopsys IP Prototyping Kits, part of the IP Accelerated initiative, center around a complete, out-of-the-box reference design that consists of a ...

411 20.0

LPDDR4 multiPHY V2 in GF (22nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

412 20.0

LPDDR4 multiPHY V2 in Samsung (14nm, 11nm, 10nm, 8nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

413 20.0

LPDDR4 multiPHY V2 in TSMC (28nm, 22nm, 16nm, 12nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

414 20.0

LPDDR4/3, DDR4/3 Memory Controller IP OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

415 20.0

LPDDR4X multiPHY in GF (14nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

416 20.0

LPDDR4X multiPHY in Samsung (14nm, 11nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

417 20.0

LPDDR4X multiPHY in TSMC (16nm, 12nm,N7, N6) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

418 20.0

LPDDR4X multiPHY Plus in GF (12nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

419 20.0

LPDDR4x/4 PHY IP for 22nm OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

420 20.0

LPDDR5/4/4X PHY in GF (12nm) The Synopsys LPDDR5/4/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in-package a...

421 20.0

LPDDR5/4/4X PHY in TSMC (16nm, 12nm, N7, N6, N5) The Synopsys LPDDR5/4/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in-package a...

422 20.0

LPDDR5X/5/4X PHY in Samsung (8nm, SF4X, SF2) The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in- package...

423 20.0

LPDDR5X/5/4X/4 combo PHY at 12nm The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...

424 20.0

GPIO 1.8V Automotive Grade 1 in GF (22nm) Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

425 20.0

GPIO 1.8V FS Automotive Grade 1 in GF (22nm) Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

426 20.0

Pre-verified Interface IP Subsystems reduce design risk and accelerate time-to-market Customers are increasingly utilizing third-party standards-based IP in their designs, but face several challenges. With more IP and more complex inter...

427 20.0

Front-end voice processing software package providing enhanced speech intelligibility for voice-enabled devices ClearVox is a software suite of advanced voice input processing algorithms aimed to enhance voice clarity in any voice-enabled device. Voice has be...

428 20.0

USB 3.0 PHY in TSMC (65nm, 55nm, 40nm, 28nm) The Synopsys USB-C™ 3.0 and USB 3.0 femtoPHY IP provide designers with a complete physical (PHY) layer IP solution for low-power mobile and consumer a...

429 20.0

DSC Decoder Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data compression and has b...

430 20.0

DSC Encoder Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data compression and has b...

431 20.0

TSMC 4nm (N4P) 1.2V/1.8V Basekit Libraries Synopsys provides system-on-chip (SoC) designers with an extensive offering of high-quality, foundation IP, including memory compilers, logic librarie...

432 20.0

TSMC 4nm (N4P) 1.2V/1.8V Basekit Libraries, multiple metalstacks Synopsys provides system-on-chip (SoC) designers with an extensive offering of high-quality, foundation IP, including memory compilers, logic librarie...

433 20.0

TSMC 4nm (N4P) 1.2V/1.8V I3C Libraries Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...

434 20.0

TSMC 4nm (N4P) 1.2V/1.8V/2.5V Failsafe GPIO Libraries Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

435 20.0

TSMC 4nm (N4P) 1.8V SD/eMMC IO Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...

436 20.0

TSMC 4nm (N4P) 1.8V SD/eMMC PHY Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...

437 20.0

TSMC 4nm (N4P) 2.5V Basekit Libraries Synopsys provides system-on-chip (SoC) designers with an extensive offering of high-quality, foundation IP, including memory compilers, logic librarie...

438 20.0

TSMC 4nm (N4P) 2.5V Basekit Libraries, multiple metalstacks Synopsys provides system-on-chip (SoC) designers with an extensive offering of high-quality, foundation IP, including memory compilers, logic librarie...

439 20.0

TSMC 5nm (N5) 1.2V/1.8V Basekit Libraries Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

440 20.0

TSMC 5nm (N5) 1.2V/1.8V Failsafe GPIO Libraries Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

441 20.0

TSMC 5nm (N5) 1.2V/1.8V Failsafe GPIO Libraries, multiple metalstacks Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

442 20.0

TSMC 5nm (N5) 1.2V/1.8V I3C Libraries Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...

443 20.0

TSMC 5nm (N5) 1.2V/1.8V/2.5V Failsafe GPIO Libraries Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

444 20.0

TSMC 5nm (N5) 1.2V/1.8V/2.5V GPIO Libraries Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

445 20.0

TSMC 5nm (N5) 1.2V/1.8V/2.5V GPIO Libraries, multiple metalstacks Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

446 20.0

TSMC 5nm (N5) 1.8V SD/eMMC IO Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...

447 20.0

TSMC 5nm (N5) 1.8V SD/eMMC PHY Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...

448 20.0

TSMC 5nm (N5) 2.5V Basekit Libraries Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...

449 20.0

TSMC 5nm (N5)1.8V SD/eMMC PHY, multiple metalstacks Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...

450 20.0

TSMC 6nm (6FF) 3.3V GPIO Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...