5251 1.0

UMC L180G 180nm Spread Spectrum PLL - 50MHz-250MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

5252 1.0

UMC L55SP 55nm Clock Generator PLL - 130MHz-650MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

5253 1.0

UMC L55SP 55nm Clock Generator PLL - 260MHz-1300MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

5254 1.0

UMC L55SP 55nm Clock Generator PLL - 520MHz-2600MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

5255 1.0

UMC L55SP 55nm DDR DLL - 150MHz-750MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

5256 1.0

UMC L55SP 55nm DDR DLL - 200MHz-1000MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

5257 1.0

UMC L55SP 55nm DDR DLL - 316MHz-1580MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

5258 1.0

UMC L55SP 55nm Deskew PLL - 130MHz-650MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

5259 1.0

UMC L55SP 55nm Deskew PLL - 260MHz-1300MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

5260 1.0

UMC L55SP 55nm Deskew PLL - 520MHz-2600MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

5261 1.0

UMC L55SP 55nm Spread Spectrum PLL - 130MHz-650MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

5262 1.0

UMC L55SP 55nm Spread Spectrum PLL - 260MHz-1300MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

5263 1.0

UMC L55SP 55nm Spread Spectrum PLL - 520MHz-2600MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

5264 1.0

UMC L65LL 65nm Clock Generator PLL - 120MHz-600MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

5265 1.0

UMC L65LL 65nm Clock Generator PLL - 240MHz-1200MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

5266 1.0

UMC L65LL 65nm Clock Generator PLL - 60MHz-300MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

5267 1.0

UMC L65LL 65nm DDR DLL - 104MHz-520MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

5268 1.0

UMC L65LL 65nm DDR DLL - 164MHz-820MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

5269 1.0

UMC L65LL 65nm DDR DLL - 78MHz-390MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

5270 1.0

UMC L65LL 65nm Deskew PLL - 120MHz-600MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

5271 1.0

UMC L65LL 65nm Deskew PLL - 240MHz-1200MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

5272 1.0

UMC L65LL 65nm Deskew PLL - 60MHz-300MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

5273 1.0

UMC L65LL 65nm Spread Spectrum PLL - 120MHz-600MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

5274 1.0

UMC L65LL 65nm Spread Spectrum PLL - 240MHz-1200MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

5275 1.0

UMC L65LL 65nm Spread Spectrum PLL - 60MHz-300MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

5276 1.0

UMC L65SP 65nm Clock Generator PLL - 130MHz-650MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

5277 1.0

UMC L65SP 65nm Clock Generator PLL - 260MHz-1300MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

5278 1.0

UMC L65SP 65nm Clock Generator PLL - 520MHz-2600MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

5279 1.0

UMC L65SP 65nm DDR DLL - 150MHz-750MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

5280 1.0

UMC L65SP 65nm DDR DLL - 200MHz-1000MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

5281 1.0

UMC L65SP 65nm DDR DLL - 316MHz-1580MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

5282 1.0

UMC L65SP 65nm Deskew PLL - 130MHz-650MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

5283 1.0

UMC L65SP 65nm Deskew PLL - 260MHz-1300MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

5284 1.0

UMC L65SP 65nm Deskew PLL - 520MHz-2600MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

5285 1.0

UMC L65SP 65nm Spread Spectrum PLL - 130MHz-650MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

5286 1.0

UMC L65SP 65nm Spread Spectrum PLL - 260MHz-1300MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

5287 1.0

UMC L65SP 65nm Spread Spectrum PLL - 520MHz-2600MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

5288 1.0

UMC L80G 80nm Clock Generator PLL - 120MHz-600MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

5289 1.0

UMC L80G 80nm Clock Generator PLL - 240MHz-1200MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

5290 1.0

UMC L80G 80nm Clock Generator PLL - 480MHz-2400MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

5291 1.0

UMC L80G 80nm DDR DLL - 129MHz-645MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

5292 1.0

UMC L80G 80nm DDR DLL - 172MHz-860MHz The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

5293 1.0

UMC L80G 80nm Deskew PLL - 120MHz-600MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

5294 1.0

UMC L80G 80nm Deskew PLL - 240MHz-1200MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

5295 1.0

UMC L80G 80nm Deskew PLL - 480MHz-2400MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

5296 1.0

UMC L80G 80nm Spread Spectrum PLL - 120MHz-600MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

5297 1.0

UMC L80G 80nm Spread Spectrum PLL - 240MHz-1200MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

5298 1.0

UMC L80G 80nm Spread Spectrum PLL - 480MHz-2400MHz The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

5299 1.0

UMC L80GOD 80nm Clock Generator PLL - 150MHz-750MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

5300 1.0

UMC L80GOD 80nm Clock Generator PLL - 300MHz-1500MHz The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...