551 20.0

Image warping IP (distortion correction IP) Built on TAKUMI's GPU IP expertise, TAKUMI’s Image Warping IP lines up hardware acceleration IP products that support a variety of different image war...

552 20.0

Image warping IP (Distortion Correction IP) Integrating advanced on-the-fly coordinate transformation and image processing powered by GPU technologies - High-performance image warping IP (distor...

553 20.0

Image warping IP core The image warping IP core TW100 builds on TAKUMI's graphics accelerator IP core family as an additional solution to a variety of distortion correcting...

554 20.0

NoC Silicon IP for RISC-V based chips supporting the TileLink protocol Truechip's NoC Silicon IP provides chip designers and architects with an efficient way to connect multiple TileLink based master and slave devices wit...

555 20.0

NoC Silicon IP for RISC-V based chips supporting the TileLink protocol Truechip's NoC Silicon IP provides chip designers and architects with an efficient way to connect multiple TileLink based master and slave devices wit...

556 20.0

Original Lossless codec IP core - Full HD 30fps@126MHz (1Sample/clk) KJN-S1 is able to get Higher performance lossless Compression by original algorithm. This product achieves a smaller circuit scale and higher compress...

557 20.0

USB4 Gen3X2 and DP1.4 X4 PHY IP with Type-C connector support M31 USB4 Gen3x2 transceiver IP provides a complete range of USB4 Gen3x2 host and peripheral applications up to 40Gbps. It is compliant with the PIPE5....

558 20.0

Multi Protocol Switch IP Core for Safe and Secure Ethernet Network "The CetraC Switch IP core is the ideal solution to interconnect any Ethernet, TSN and ARINC 664 Part 7 (AFDX) equipment for safety critical applicati...

559 20.0

Multi Protocol Switch IP Core for Safe and Secure Ethernet Network "The CetraC Switch IP core is the ideal solution to interconnect any TSN, Ethernet and ARINC 664 Part 7 (AFDX) equipment for safety critical applicati...

560 20.0

DVB-S2 LDPC BCH Decoder and Encoder IP Core The DVB-S2 LDPC-BCH block is a powerful FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite....

561 20.0

DVB-S2X LDPC BCH Decoder and Encoder IP Core The DVB-S2X LDPC Decoder is a powerful FEC core decoder for Digital Video Broadcasting via Satellite. It implements extensions to the DVB-S2 design fo...

562 18.0

Bluetooth® Bluetooth Low Energy 6.2 PHY IP The icyTRX-LE-22 is a compact, ultra-low-power Bluetooth® Low Energy 6.2 PHY IP core developed in 22nm CMOS technology. It is engineered for seamless ...

563 17.5

802.11ax STA mode IP This IP includes a recommendation-compliant 802.11ax PHY layer C floating-point code for the Station (STA) mode. The code is integrated into a simulat...

564 17.5

Wi Fi PHY TestBench IP This datasheet present s the verification e nvironment of Comsis IEEE 802.11n PHY IP, including a SystemVerilog test bench. This environment allows 2x...

565 15.0

High Bandwidth Memory 3 (HBM3/3E) IP optimized for Samsung SF4X SkyeChip’s HBM3 IP consists of a PHY and memory controller optimized for Samsung SF4X process to support the HBM3 memory standard (JESD238A) operating...

566 15.0

TSMC 13.1Gbps Multi-Protocol Low-Power SerDes IP It is a 4-lane Serializer/Deserializer IP supporting data rates from 500Mbps to 13.1Gbps. It features flexible architecture for multiple high-speed se...

567 15.0

TSMC 25Gbps SerDes IP with Equalizer This is a high-performance, multi-protocol serial transceiver IP that supports data rates from 1Gbps to 26Gbps. Built on TSMC 12nm technology, it is d...

568 15.0

DVB-S2X Wideband LDPC BCH Encoder IP Core The DVB-S2X Wideband LDPC BCH Encoder IP Core is developed for Digital Video Broadcasting applications....

569 14.0

TicoXS FIP UHD4K Encoder / Decoder IP-core with JPEG XS and Flawless Imaging Profile (FIP) - – The newest codec for AV over IP with 100% quality and zero latency ! TicoXS FIP is the smart path to AV over IP. With low logic & low memory, it delivers together the interoperable JPEG XS lightweight low latency compre...

570 14.0

TicoXS FIP UHD8K Encoder / Decoder IP-core with JPEG XS and intoPIX Flawless Imaging Profile (FIP) – The newest codec for AV over IP with 100% quality and zero latency ! TicoXS FIP is the smart path to AV over IP. With low logic & low memory, it delivers together the interoperable JPEG XS lightweight low latency compre...

571 12.0

PCI Express PHY serial link PIPE Transceiver IP cell/hard macro SMS5000 is a fully integrated CMOS transceiver that handles the full Physical Layer PCI Express protocol and signaling. It contains all necessary AFE ...

572 12.0

Serial ATA (SATA) I/II PHY IP CORE SMS6000 is a Serial ATA gen I and gen II compliant PHY IP which supports SAPIS and Serial Attached SCCI (SAS) specifications both at 1.5 Gbp/s and 3.0...

573 12.0

WiSUN Sub-GHz 433, 868, 915MHz Transceiver IP The ShortLink Sub-GHz Transceiver RF IP 'SL40LP_Sub1GHzTrx_2' is a complete mixed signal RF IP for the 433, 868 and 915MHz frequency bands. It is comp...

574 12.0

Sub-GHz 433MHz RF Transceiver IP The ShortLink Sub-GHz Transceiver RF IP 'SL150_433MHzTrx_1' is a complete mixed signal RF IP for the 433MHz frequency band. It offers a data rate of 1...

575 10.0

H.264 Compression Video Over IP - HD Encoder Subsystem This Video Over IP Subsystem integrates H.264 compression Transport Stream and RTP/UDP/IP encapsulation to enable the rapid development of complete vi...

576 10.0

H.264 Decompression Video Over IP – HD Decoder Subsystem This Video Over IP Subsystem integrates H.264 Decompression, Transport Stream and RTP/UDP/IP de-capsulation to enable the rapid development of complet...

577 10.0

64x8 Bits OTP (One-Time Programmable) IP, UM- 55nm ULP standard CMOS core logic Process The AT64X8U55ULP6AA is organized as a 64-word by 8 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in 55nm ULP standard ...

578 10.0

64x8 Bits OTP (One-Time Programmable) IP, X-FA- 0.18μm XH018 Modular Mixed Signal Process The ATO00064X8XH180TG33NA is organized as a 64-bit by 8 one-time programmable (OTP). This is a type of non-volatile memory fabricated in X-FA- 0.18μm ...

579 10.0

256x8 Bits OTP (One-Time Programmable) IP, TSM- 22ULP 0.8V/1.8V process The AT256X8T22ULP6AA is organized as 256 bits by 8 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in TSM- 22nm ULP CMOS...

580 10.0

768x39 Bits OTP (One-Time Programmable) IP, TSM- 55ULP 0.9V–1.2V / 2.5V Process The ATO0768X39TS055ULP4NA is organized as 768x39 one-time programmable (OTP). This is a type of non-volatile memory fabricated in TSM- 55nm LP 1.2V/2....

581 10.0

16Kx33 Bits OTP (One-Time Programmable) IP, TSM- 40LP 1.1V/2.5V Process The ATO016KX33TS040LLP7ZA is organized as 16K-bits by 33 one-time programmable (OTP). This is a type of non-volatile memory fabricated in TSM- 40nm ...

582 10.0

H8/300 CPU IP ( 8-bit CPU IP ) H8/300 is a high speed 8-bit CPU with an internal 16-bit architecture. H8/300 CPU IP is compatible with H8S CPU subsystem IP (H8S C200) on system, bus...

583 10.0

H8S CPU subsystem (H8S C200) IP H8S is a high speed 16-bit CPU with an internal 32-bit architecture, which is upward-compatible with H8/300 and H8/300H CPUs on an object level. This ...

584 10.0

H8SX CPU subsystem (H8SX C3000) IP H8SX is a high speed 32-bit CPU, which is upward-compatible with H8/300, H8/300H and H8S CPUs on an object level. This subsystem IP supports many and ...

585 10.0

Camera ISP IP (Competitive Performance) - ZELKOVA Zelkova is a comprehensive ISP IP that includes many functionalities for image processing applications. It is optimized for low light environment appl...

586 10.0

Camera ISP IP (High Performance) - METASEQUOIA METASEQUOIA is a comprehensive ISP IP that includes many functionalities for image processing. It is optimized for high resolution and low light envir...

587 10.0

PCI Express - Configurable PCI Express 4.0 IP The Renesas PCIe 4.0 Dual Mode Link Controller IP is compliant with the "PCI Express (PCIe) 4.0 Base Specification". This IP supports the major functi...

588 10.0

Secure-IC's Securyzr™ Inline Decrypter IP Core The Inline Decrypter IP Core enables on-the-fly execution of encrypted code from Flash. It is often used to protect the source code from decompiling o...

589 10.0

JESD204D - Succesfully Taped out, Silicon Agnostic IP core The JESD204D Controller IP is based on the recently released D revision of the JEDEC standard for Serial Interface for Data Converters. The JESD204D I...

590 10.0

Digital Physical Unclonable Function (PUF) IP Our Digital PUF IP is a digital version of our quantum-based PUF IP (see QDID). The Logic-based Digital PUF IP is a strong hardware root-of-trust for ...

591 10.0

MIPI DSI-2 Transmitter Interface IP MIPI DSI-2 (Display Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile dev...

592 10.0

MIPI I3C Controller and Target fully featured IP solution The MIPI I3C Controller IP is a highly optimized and technology-agnostic implementation of the MIPI I3C v.1.1.1 standard targeting both ASIC and F...

593 10.0

Direct Memory Access DMA Controller IP Core The DMA_CTRL core implements a low-power, single-channel Direct Memory Access (DMA) controller that is used to transfer data across a bus to and from ...

594 10.0

Visibility Improver IP “LucidEye” improves the visibility of unclear images such as those deteriorated due to weather conditions (snow, haze, or fog), and dark images due t...

595 10.0

4Kx16 Bits OTP (One-Time Programmable) IP, UM- 110 nm 1.2V/3.3V L110AE Process The AT4K16U110MAE0DA is organized as a 4K-bits by 16 one-time programmable memory. This is a kind of non-volatile memory fabricated in UM- L110AE proc...

596 10.0

4Kx32 Bits OTP (One-Time Programmable) IP, TSM- 40nm ULP 1.1V/2.5V Process The AT4K32T40ULP7ZC is organized as 4K-bits by 32 one-time programmable (OTP). This is a type of non-volatile memory fabricated in TSM- 40nm ULP stand...

597 10.0

4Kx8 Bits OTP (One-Time Programmable) IP, GLOBA-FOUNDR---® 22nm FDX 0.8V/1.8V Process The AT4K8G22FDX0AA is organized as a 4K-bits by 8 one-time programmable memory. This is a kind of non-volatile memory fabricated in GLOBA-FOUNDR---® ...

598 10.0

8Kx8 Bits OTP (One-Time Programmable) IP, VI- 0.15µm 1.8V/5V BCD GIII Process The AT8K8V150BCD0DB is organized as an 8K-bit by 8 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in VI- 0.15μm BCD GII...

599 10.0

UniPro 1.6 Host/Device IP The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...

600 10.0

UniPro 1.8 Host/Device IP The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...