Design & Reuse
Catalog of SIP Cores
System on Chip design resources
5506 IP
701
50.0
40G UCIe PHY for high-density advanced packages
Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI,...
702
50.0
40G UCIe PHY for organic substrate standard packages
Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI,...
703
50.0
12-bit, 5 GSPS Digital-to-Analog Converter (DAC) IP block GlobalFoundries 22nm
The D12B5G is a low-power, high-speed digital to analog converter (DAC) intellectual property (IP) block. It is a current-steering DAC that has a 1...
704
50.0
12-bit, 500 MSPS Digital-to-Analog Converter (DAC) IP block GlobalFoundries 55nm
The D12B500M is an ultra low-power, high-speed digital to analog converter (DAC) intellectual property (IP) block. It is a current steering DAC that h...
705
50.0
12-bit, 9 GSPS High Performance Swift™ DAC in 16nm CMOS
The ODT-DAC-12B9G-16 is a high performance current steering 12-bit 9GSPS DAC on 16nm CMOS process that operates at an update rate of up to 9GSPS. The ...
706
50.0
32G PHY in TSMC (16nm, 12nm, N7, N6, N6C, N5, N5A, N4C, N3E, N3P,N2P)
The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and ...
707
50.0
56G Ethernet PHY in TSMC (16nm, 12nm)
The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security M...
708
50.0
WAVE-J, 8-bit, 12-bit JPEG Codec IP upto 64Kx64K New!
Chips&Media WAVE-J is a standalone and high-performance JPEG codec IP that can perform JPEG Baseline/Extended and MJPEG decoding and encoding. Com...
709
50.0
WAVE517, AV1, H.265, HEVC, H.264, AVC, VP9, AVS2 video decoder IP for 4K
The world-leading hardware IP provider, Chips&Media, pre-released the multi-standard HW IP named WAVE517, targeting 4K ultra-high-definition (UHD), wh...
710
50.0
WAVE521C, H.265, HEVC, H.264, AVC video codec IP for 4K
WAVE521C is a 4K multi-format codec IP to support both HEVC/H.265 and AVC/H.264 video standards. This IP core provides real-time performance for encod...
711
50.0
WAVE627, AV1, H.265, HEVC, H.264, AVC, video encoder IP for 4K
WAVE627 is a 4K multi-standard video encoder HW IP that supports AV1, HEVC/H.265, and AVC/H.264 video codec standards. It provides 4K60fps@500MHz real...
712
50.0
WAVE633, H.265, HEVC, H.264, AVC, video codec IP for 4K
WAVE633 is a 4K multi-standard video codec HW IP that supports HEVC/H.265 and AVC/H.264 video codec standard. It provides 4K60fps@500MHz real-time enc...
713
50.0
HBM3 PHY V2 in TSMC (N5, N4P, N3E)
The Synopsys HBM3 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking ASIC...
714
50.0
PCIe 4.0 PHY in TSMC (28nm, 16nm, 12nm, N7, N3P, N3E, N2P)
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
715
50.0
PCIe 5.0 PHY in TSMC (16nm, 12nm, N7, N6, N6C, N5, N4P, N4C, N3E, N3P, N2P)
The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s applicatio...
716
50.0
PCIe 6.0 Controller IP
The Wolley PCI Express® (PCIe®) Controller IP is a highly configurable, performance-optimized core designed for ASIC and FPGA integration. Supporting ...
717
50.0
PCIe Gen3 to SRIO Gen3 Bridge (FPGA)
Mobiveil’s PCIe Gen3 to SRIO Gen3 Bridge is a high-performance FPGA-based protocol conversion IP that enables seamless communication between PCI Expre...
718
50.0
PCIe Gen5 NVMe SSD RAMDISK Reference Platform
Mobiveil’s RAMDISK-Gen5is a PCIe Gen5 and 1.4 NVMe compliant Ramdisk that emulates the next generation NVMe Gen5 SSDs with high performance. With hi...
719
50.0
HDMI 2.1 Tx PHY in TSMC (16nm, 12nm, N7, N6, N6C, N4, N3E)
The Synopsys HDMI 2.1 TX Controller and PHY IP solutions,compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the...
720
50.0
HDMI 2.1/DisplayPort 2.1 TX PHY in TSMC (N3E, N3P)
The Synopsys HDMI 2.1 TX Controller and PHY IP solutions,compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the...
721
50.0
DDR5 PHY in TSMC (N5, N4P, N4C, N3P, N3E)
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...
722
50.0
Ceva-Waves Bluetooth 5.4 dual mode Baseband Controller
Ceva-Waves Bluetooth 5.4 dual mode IP is a complete and flexible solution for integration into SoCs/ASSPs. It contains both "classic" BR/EDR Bluetoot...
723
50.0
Ceva-Waves Bluetooth 6.0 dual mode Baseband Controller
Ceva-Waves Bluetooth dual mode IP is a complete and flexible solution for integration into SoCs/ASSPs. It has been qualified for Bluetooth Core Specif...
724
50.0
5G Baseband Platform IP for Mobile Broadband and IoT
PentaG2™ is Ceva’s second generation 5G NR baseband modem IP platform. It is the industry’s only platform offering capable of meeting the extreme perf...
725
50.0
AHB Octal SPI Controller with PSRAM and XIP Support
The Silvaco Octal SPI Memory Controller IP core is a serial peripheral interface (SPI) master which controls an external serial device, usually an ind...
726
50.0
High Performance DDR5/4/3 Memory Controller
Mobiveil's DDR5/4/3 Memory Controller is a highly flexible and configurable design targeted for high performance enterprise server and real-time consu...
727
50.0
MIPI C-PHY v1.0 D-PHY v1.2 TX 2 trios/2 Lanes in TSMC (12nm, N5, N3P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
728
50.0
MIPI C-PHY v1.0 D-PHY v1.2 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
729
50.0
MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N4, N4P, N3E, N3P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
730
50.0
MIPI C-PHY v2.0 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (N7, N6, N5, N4, N4C, N3E, N3P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
731
50.0
MIPI C-PHY v2.0 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (N6, N6C, N5, N4P, N4C, N3)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
732
50.0
MIPI M-PHY G4 Type 1 2Tx2RX in TSMC (16nm, 12nm, N7, N6, N5, N4, N3A, N3E)
The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI M-PHY v5.0 specification, supports speeds up to 23.32 Gbps per lane. The I...
733
50.0
Ultra High-Speed Cache Memory Compiler
Silvaco’s Ultra High-Speed cache memory is an adaptable, independent, non-coherent cache Intellectual Property (IP) featuring an advanced cache ar...
734
50.0
Modern, high performance Audio DSP, optimized for far-field noise reduction and Artificial Intelligence speech recognition
The Ceva-BX2 audio/voice DSP is targeted for high performance audio devices such as DTV, Smart Speaker, Soundbar, and car infotainment systems. Ceva-...
735
50.0
Low-power, high-speed 12-bit 4GSPS SAR (ADC) TSMC 28nm HPC+
The A12B4G is a low-power, high-speed analog to digital converter (ADC) intellectually property (IP) design block. It is a time interleaved (TI) succe...
736
50.0
Low-power, high-speed 12-bit, 8 GSPS Analog to Digital Converter (ADC) IP block TSMC 28nm HPC+ process
The A12B8G is a low-power, high-speed analog to digital converter (ADC) intellectually property (IP) design block. It is a time interleaved (TI) succe...
737
50.0
LPDDR5/4x/4 combo PHY on 14nm, 12nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
738
50.0
LPDDR5X/5/4X PHY in TSMC (N5, N4P, N4C, N3E, N3P, N3A)
The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in- package...
739
50.0
Open RAN Platform for Base Station and Radio
Industry’s First Comprehensive 5G Baseband Platform IP for 5G RAN ASICs and Open RAN Building on more than a decade of leadership in baseband IP solut...
740
50.0
USB 2.0 nanoPHY in SMIC (65nm)
The Synopsys USB 2.0 nanoPHY provides designers with a complete Physical Layer (PHY) IP solution, designed for low-power mobile and consumer applicati...
741
50.0
USB 3.1 PHY (10G/5G) inTSMC (16nm, 12nm, N7, N6, N5,N3E, N3P)
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offerin...
742
50.0
USB-C 3.1 DP/TX PHY ebdaux in TSMC (N6C, N5, N4P, N4C, N3E)
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offerin...
743
50.0
USB-C 3.2 DP/TX PHY in TSMC (N3E)
The Synopsys USB-C 3.2/DisplayPort 1.4 IP solution consists of USB-C 3.2/DisplayPort 1.4 PHYs, USB-C 3.2/DisplayPort 1.4 controllers (Device, Host, or...
744
50.0
USB-C 3.2 SS/SSP PHY in Type-C in TSMC (N7, N6, N5, N3E)
The Synopsys SuperSpeed 3.2 USB IP solution is based on the USB 3.2 specification from the USB Implementer Forum. The USB 3.2 IP offering includes con...
745
50.0
TSMC 3nm (N3E) 1.2V LVDS
Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...
746
50.0
TSMC 3nm (N3E) 1.2V/1.8V GPIO Libraries
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
747
50.0
TSMC 3nm (N3E) 1.2V/1.8V GPIO with 1.8V Failsafe Libraries
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
748
50.0
TSMC 3nm (N3E) 1.2V/1.8V GPIO with 1.8V Failsafe Libraries, multiple metalstacks
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
749
50.0
TSMC 3nm (N3E) 1.2V/1.8V I3C Libraries
Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...
750
50.0
TSMC 3nm (N3E) 1.2V/1.8V I3C Libraries, multiple metalstacks
Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...