Design & Reuse
Catalog of SIP Cores
System on Chip design resources
5513 IP
1251
10.0
Wide Range Multi-Output PLL - TSMC CLN7FF
Analog Bits’ Wide Range Multi-Output PLL addresses a large portfolio of applications, ranging from simple clock de-skew and non-integer clock multipli...
1252
10.0
Wide Range PLL - GLOBALFOUNDRIES 65 65G
Analog Bits Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de-skew and non-integer clock multiplication to prog...
1253
10.0
Wide Range PLL - TSMC 6FF
Analog Bits’ Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de-skew and non-integer clock multiplication to pro...
1254
10.0
Wide Range PLL - TSMC CLN3P
Analog Bits’ Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de- skew and non-integer clock multiplication to p...
1255
10.0
Wide Range PLL - TSMC N5
Analog Bits’ Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de-skew and non-integer clock multiplication to pro...
1256
10.0
Wide Range Programable Integer PLL - TSMC CLN2P
Analog Bits’ Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de- skew and non-integer clock multiplication to p...
1257
10.0
Die-to-Die Controller IP
The Synopsys Die-to-Die Controller IP, optimized for latency, bandwidth, power and area, enables efficient inter-die connectivity in server, AI accele...
1258
10.0
Die-to-Die, 112G Ultra-Extra Short Reach PHY in GF (12nm)
The Synopsys XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip modul...
1259
10.0
Die-to-Die, 112G Ultra-Extra Short Reach PHY in TSMC (12nm, N7, N6, N5)
The Synopsys XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip modul...
1260
10.0
Differential Clock Receiver - TSMC CLN2P
Analog Bits’ Differential Clock Receiver macro addresses a large portfolio of applications. The Receiver is designed for digital logic processes and u...
1261
10.0
Differential Clock Receiver - TSMC CLN3A
Analog Bits’ Differential Clock Receiver macro addresses a large portfolio of applications. The Receiver is designed for digital logic processes and u...
1262
10.0
Differential Clock Receiver - TSMC CLN3E
Analog Bits’ Differential Clock Receiver macro addresses a large portfolio of applications. The Receiver is designed for digital logic processes and u...
1263
10.0
Differential Clock Receiver to CML - TSMC CLN2P
Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...
1264
10.0
Differential Clock Receiver to CML - TSMC CLN3A
Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...
1265
10.0
Differential Clock Receiver to CML - TSMC CLN3E
Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...
1266
10.0
Differential Clock Receiver to CML - TSMC CLN6FF
Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...
1267
10.0
Differential Clock Reciever - TSMC CLN3P
Analog Bits’ Differential Clock Receiver macro addresses a large portfolio of applications. The Receiver is designed for digital logic processes and u...
1268
10.0
Differential Clock Reciever to CML - TSMC CLN3P
Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...
1269
10.0
Differential Output Buffer - TSMC CLN3P
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a...
1270
10.0
Differential Output Buffer - TSMC 6FF
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...
1271
10.0
Differential Output Buffer - TSMC CLN3E
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...
1272
10.0
Differential Output Buffer - TSMC CLN3P
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...
1273
10.0
Differential Output Buffer - TSMC CLN4P
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...
1274
10.0
Differential Output Buffer - TSMC N5
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...
1275
10.0
Differential Output Driver - TSMC CLN2P
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...
1276
10.0
Differential Receiver - TSMC 7FF
Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...
1277
10.0
Differential Signal Receiver - TSMC 6FF
Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...
1278
10.0
Differential Signal Receiver - TSMC N5
Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...
1279
10.0
High Performance 1-22.5G PCIe4/SAS4 PHY - TSMC 16FFC
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
1280
10.0
High Performance 20GHz C2C PLL - TSMC CLN3A
Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...
1281
10.0
High Performance 20GHz C2C PLL - TSMC CLN3E
Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...
1282
10.0
High Performance 20GHz C2C PLL - TSMC CLN6FF
Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...
1283
10.0
High Performance 20GHz PLL - TSMC CLN4P
Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...
1284
10.0
High Performance 20GHz PLL - TSMC CLN5A
Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...
1285
10.0
High Precision Temp Sensor - TSMC CLN2P
Analog Bits' High Accuracy Thermometer is a highly integrated macro for monitoring temperature variation on-chip, allowing very high precision even in...
1286
10.0
High Precision Temp Sensor - TSMC CLN3A
Analog Bits' High Accuracy Thermometer is a highly integrated macro for monitoring temperature variation on-chip, allowing very high precision even in...
1287
10.0
High Precision Temp Sensor - TSMC CLN3E
Analog Bits' High Accuracy Thermometer is a highly integrated macro for monitoring temperature variation on-chip, allowing very high precision even in...
1288
10.0
High Precision Temp Sensor - TSMC CLN5A
Analog Bits' High Accuracy Thermometer is a highly integrated macro for monitoring temperature variation on-chip, allowing very high precision even in...
1289
10.0
High Speed 20GHz PLL - TSMC CLN6FF
Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...
1290
10.0
High Speed PLL - TSMC N4P
Analog Bits’ High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous...
1291
10.0
High Speed PLL - TSMC N5
Analog Bits’ High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous...
1292
10.0
High Speed PLL - TSMC N5A
Analog Bits’ High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous...
1293
10.0
High Speed PLL - TSMC N5A
Analog Bits’ High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous...
1294
10.0
High Speed PLL CML to Complementary - TSMC CLN3P
Analog Bits’ High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous...
1295
10.0
TileLink Target
TileLink is a chip-scale connection standard that enables many masters to have synchronised memory mapped access to memory and other slave devices. Ti...
1296
10.0
LIN Bus Master/Slave Controller Core
Implements a communication controller that transmits and receives complete Local Interconnect Network (LIN) frames to perform serial communication acc...
1297
10.0
MIPI C-PHY v1.2 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (16nm) for Automotive
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
1298
10.0
MIPI C-PHY v1.2 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (16nm, N7) for Automotive
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
1299
10.0
MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm) for Automotive
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
1300
10.0
MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A, N3A)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...