51 12.0

JESD204b Ser PHY GF 22FDX/ GF 22FDX-PLUS InCirT offers Serializer PHY that is implemented in Global Foundries 22FDX CMOS technology. The IP macro offers 1x lane with data rates from 6.375 Gbp...

52 12.0

Ultra-low jitter, high SFDR LC-based PLL-12.5GHz for JESD204C-B12 INCIRT’s LCPLL12p5GGF22 is an LC-oscillator-based charge-pump PLL which provides ultra-low jitter (250fs rms jitter in 1kHz-100MHz of integration band...

53 12.0

Ultra-low jitter, low-power ring-oscillator-based PLL-3GHz-4GHz InCirT’s AIX-PLL-4G-GF22DFX is a ring-oscillator-based analog-PLL that provides ultra-low jitter (3 ps RMS at 4GHz) and low power consumption (4.5 mW ...

54 10.0

IEEE1588 & IEEE802.1AS PTP Hybrid Clock (HC) core The PTP Hybrid Clock (HC) from NetTimeLogic is a combination of NetTimeLogic's PTP Transparent Clock (TC) and PTP Ordinary Clock (OC). It adds the Syn...

55 10.0

IEEE1588 & IEEE802.1AS PTP Timestamp Unit (TSU) core NetTimeLogic’s PTP Timestamp Unit is an implementation of a single port Frame Timestamp Unit (TSU) according to IEEE1588-2008 (PTP). It detects PTP fr...

56 10.0

NTP Server core NetTimeLogic’s NTP Server is a full hardware (FPGA) only implementation of a SNTPv4 Server according to RFC 4330/5905. It supports hardware timestampi...

57 8.0

11-bit, 1GSPS, ultra-low power IQ-DAC in 22nm IQDAC1GGF22FDX is an ultra-low power current-steering 11-bit IQDAC which can operate up to 1GSPS designed in GF 22nm FDX. It consists of two DACs (I a...

58 8.0

11-bit, 500MSPS, ultra-low power IQ-DAC in 22nm IQDAC500GF22FDX is an ultra-low power current-steering 11-bit IQDAC which can operate up to 500MSPS designed in GF 22nm FDX. It consists of two DACs (...

59 8.0

11-bit, up-to 2GHz iBW, ultra-low power DAC in GF 22nm Tx2GGF22 is the flagship product of InCirT exploiting completely a new architecture which leads to ultra-low power consumption (0.4W) while maintainin...

60 8.0

Low jitter, low-power clock-deskew PLL operating from 6GHz to 9.5GHz InCirT’s CDPLLGF22 is a ring-oscillator-based clock-deskew PLL designed for low jitter and low power consumption, operating within a frequency range o...

61 8.0

Low jitter, ultra-low power (<950uW) ring-oscillator-based PLL-2.4GHz InCirT’s APLL2p4GGF22 is the ring-oscillator based analogue-PLL which provides low jitter (1ps rms jitter at 2.4GHz) and low-power consumption (<950uW...

62 8.0

Low power, 500MSPs, 9-bit time-based two-step ADC The Time-Based ADC from InCirT is a compact, low-power 9-bit analog-to-digital converter designed in GF 22FDX CMOS technology. The design combines a t...

63 5.0

Time Sensitive Networking (TSN) IIC(R) Plugfest Application core The TSN Industrial Internet Consortium(R) (IIC) Plugfest Application is a companion core for the TSN IP cores from NetTimeLogic. The IIC(R) Plugfest A...

64 5.0

NTP Client core NetTimeLogic’s NTP Clientis a full hardware (FPGA) only implementation of a SNTPv4 Client according to RFC 4330/5905. It supports hardware timestampin...

65 5.0

Synchronous Ethernet (SyncE) ESMC and Enhanced ESMC core NetTimeLogic’s Synchronous Ethernet (SyncE) Node is a full hardware (FPGA) only implementation of an ESMC frame Handler and State selector. The whole ...

66 4.0

Adjustable Counter Clock core The Adjustable Clock from NetTimeLogic is an adjustable counter clock with nanosecond resolution (second and nanosecond format). It is used by all oth...

67 4.0

ISP, Image Signal Procesing, Real-time Pixel Processor Automotive Dream Chips Real-time Pixel Processor (RPP) is a scalable and configurable High Dynamic Range (HDR) capable image signal processor (ISP), developed fo...

68 4.0

ISP, Image Signal Processing, Real-time Pixel Processor for Automotive Dream Chip’s Real-time Pixel Processor (RPP) is a scalable and configurable High Dynamic Range (HDR) capable image signal processor (ISP), develo?ped ...

69 3.0

Ultra-low jitter, type-I ADDLL with adaptive dither cancellation-3GHz-5GHz InCirT’s Type-I ADDLL5GGF22 is an all-digital delay-locked loop (ADDLL) featuring an adaptive dithering cancellation technique. This innovation ensure...

70 2.0

NMEA Time of Day (ToD) Slave core NetTimeLogic’s NMEATime Of Day (ToD) Slave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to a Time...

71 2.0

IRIG-B Slave core NetTimeLogic’s IRIG Slave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to an IRIG-B004, B005, B00...

72 2.0

Pulse Per Second Slave (PPS) core NetTimeLogic’s PPS Slave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to a Pulse per Second input...

73 1.0

Radio Clock (DCF77) Master core NetTimeLogic’s DCF Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize other nodes via DCF signal...

74 1.0

Radio Clock (DCF77) Slave core NetTimeLogic’s DCFSlave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to a DCF signal encoded as P...

75 1.0

Capacitor-less Low Dropout regulator (LDO) 30 mA output The ICPMLDO101_GF22FDX is capacitor-less linear voltage regulator in GF 22nmFDX. The LDO operates for a single input voltage in the range 1.4V to 1.9V...

76 1.0

Real Time Clock (RTC) Master core NetTimeLogic’s RTC Master Clock is a full hardware (FPGA) only implementation of a synchronization core allowing to read and write a I2C Realtime Cloc...

77 1.0

Time aligned Frequency Generator core The Frequency Generator from NetTimeLogic is a clock aligned frequency generator allowing any frequency to be generated between 1Hz and 10MHz adjustab...

78 1.0

Time aligned Signal Generator core The Signal Generator from NetTimeLogic is a clock aligned pulse and pattern (PWM) generator with nanosecond resolution (second and nanosecond format)....

79 1.0

Time aligned Signal Timestamper core The Signal Timestamper from NetTimeLogic is a timestamper with nanosecond resolution (second and nanosecond format). It uses NetTimeLogic's Adjustable...

80 1.0

NMEA Time of Day (ToD) Master core NetTimeLogic’s Time Of Day (ToD) Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize a Time of Da...

81 1.0

Low-Power, High-Accuracy, Bandgap Reference in GF22FDX Our ICPMBGR01_GF22FDX is a high precision voltage and current reference circuit that consumes ultra-low power from a single supply. Moreover, ICPMBGR0...

82 1.0

IRIG-B Master core NetTimeLogic’s IRIG Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize other nodes via IRIG-B007...

83 1.0

Pulse Per Second (PPS) Clock to PPS core NetTimeLogic’s PPS Clock to PPS core is a full hardware (FPGA) only implementation of a PPS generator out of a clock of configurable frequency, it is ...

84 1.0

Pulse Per Second Master (PPS) core NetTimeLogic’s PPS Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize other nodes to a Pulse per...

85 0.0

a robust lighting control technology based on the globally interoperable Bluetooth mesh standard. We provide a robust lighting control technology based on the globally interoperable Bluetooth mesh standard. Whether you are a component manufacturer,...

86 0.0

8-bit MCU The DF6811 is an advanced 8-bit MCU IP Core, with highly sophisticated, on-chip peripheral capabilities. DF6811 soft core is binary-compatible with th...

87 0.0

V-by-One Rx IP, Silicon Proven in 40G Using internal equipment connections, the V-by-One HS technology seeks to send video signals at a high data rate. The V-by-One HS Standard outlines th...

88 0.0

V-by-One Rx IP, Silicon Proven in SMIC 40LL The V-by-One HS technology aims to transmit video signals at a high data rate using internal equipment connections. The requirements to create a trans...

89 0.0

V-by-One Tx IP, Silicon Proven in 40G The V-by-One HS technology aims to transmit video signals at a high data rate using an internal connection between devices. The requirements to create...

90 0.0

V-by-One Tx IP, Silicon Proven in SMIC 40LL V-by-One HS technology targets a high-speed data transmission of video signals based on the internal connection of equipment. V-by-One® HS Standard de...

91 0.0

V-by-One/ LVDS Tx IP, Silicon Proven in SMIC 40LL The V-by-One® HS technology aims to transmit video signals at a high data rate using internal equipment connections. The requirements to create a tran...

92 0.0

V-by-One/LVDS Rx IP, Silicon Proven in GF 22FDX The V-by-One® HS technology aims to transmit video signals at a high data rate using internal equipment connections. The requirements to create a tran...

93 0.0

V-by-One/LVDS Rx IP, Silicon Proven in SMIC 40LL V-by-One® HS technology targets a high-speed data transmission of video signals based on internal connection of equipment. V-by-One® HS Standard defin...

94 0.0

V-by-One/LVDS Tx Combo PHY, Silicon Proven in 28HPC+ V-by-One/ LVDS Tx Combo PHY IP Core aims at achieving high-speed data transmission for video signals through internal equipment connections. The V-by-...

95 0.0

V-by-One/LVDS Tx IP, Silicon Proven in GF 22FDX Based on internal equipment connections, the V-by-One® HS technology aims to transmit video signals at high data rates. The requirements to build a tr...

96 0.0

v-CNNDesigner tool The new v-CNNDesigner tool automatically translates trained neural networks into optimized implementations that run efficiently on the v-MP6000UDX arc...

97 0.0

D-MAC-10/100 Our innovative solution is a hardware implementation of media access control protocol defined by the IEEE standard. DMAC in cooperation with external ...

98 0.0

v-MP6000UDX - Deep Learning and Vision Processor The videantis processor is the most power-efficient and highest-performing visual processing architecture that you can license on the market. Whether ...

99 0.0

v-MP6000UDX processor Deep learning has quickly become a must-have technology to bring new smart sensing and intelligent analysis capabilities to all of our electronics. Wh...

100 0.0

H.264 Audio & Video Decoder IP The H.264 Decoder IP Core is a full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The H.264 ...