Design & Reuse
5377 IP
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PCIe 3.0, 2.1, 1.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
Rambus PCIe 3.0 Controller is a highly configurable PCIe 3.0 interface Soft IP designed for ASIC and FPGA implementations supporting endpoint, root po...
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PCIe 4.0 Controller with AMBA AXI interface
Rambus PCIe 4.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The Rambus PCIe 4.0 Contr...
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PCIe 5.0 Controller with AMBA AXI interface
Rambus PCIe 5.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 5.0 Controlle...
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PCIe 7.0 Controller with AXI
The Rambus PCI Express® (PCIe®) 7.0 Controller with AXI is a configurable and scalable design for ASIC implementations. It is backward compatible to P...
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PCIe Controller Testbench
PCIe Testbench from Rambus emulates a Root Complex device enabling simulation of a PCI Express design. This includes the following features: • R...
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PCIe Switch for USB4 Hubs, Hosts and Devices
Rambus PCIe Multi-port Switch for USB4 is a customizable, embedded Switch for PCI Express (PCIe) designed for implementations in USB4 devices. A fully...
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VDC-M (VESA Display Compression-M) Decoder
The Rambus VESA VDC-M 1.2 Decoder IP Core (formerly from Hardent) implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 decoder to deliv...
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VDC-M (VESA Display Compression-M) Encoder
The Rambus VESA VDC-M 1.2 Encoder IP Core (formerly from Hardent) implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 encoder to deliv...
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HDCP Engine
The EIP-116 High-bandwidth Digital Content Protection Control Path module provides the required technology for implementing all the secure access, cry...
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HDMI 2.1 Forward Error Correction (FEC) Receiver
The HDMI Forward Error Correction (FEC) Receiver IP Core implements Reed-Solomon FEC and symbol de-interleaving/de-mapping as specified by the HDMI 2....
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HDMI 2.1 Forward Error Correction (FEC) Transmitter
The HDMI Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol mapping/interleaving as specified by the HDMI 2.1 ...
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DDR3 Memory Controller
Rambus’s DDR3 Controller Core offered by Rambus is designed for use in applications requiring high memory throughput, high clock rates and full progra...
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DDR4 Memory Controller
Rambus DDR4 Controller Core from Rambus is designed for use in applications requiring high memory throughput, high clock rates and full programmabilit...
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Read-Modify-Write Core
The Read-Modify-Write (RMW) Core from Rambus handles misaligned bursts when an Error Correction Code (ECC) is being used. An ECC code word must be ca...
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Mem Test Analyzer Core
The Rambus Mem Test Analyzer Core from Rambus is used to capture the results from Rambus Memory Test Core. The Mem Test Analyzer Core can be used in ...
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Reorder Core
The Reorder Core from Rambus reorders requests based on first on priority and second on throughput optimization. Throughput optimization includes m...
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AES + SHA DMA Crypto Accelerator
The EIP-120 is a low-power low-gatecount crypto core with DMA capability and local key storage. Compared to a software only solution, the core provide...
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AES Key Wrap Crypto Accelerator
The EIP-37 is the IP for accelerating the AES Key Wrap cipher algorithm (NIST-Key-Wrap & RFC3394). Designed for fast integration, low gate count and f...
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AES-ECB 1 Billion Trace DPA & Fault Injection Resistant Crypto Accelerator
Rambus DPA & Fault Injection Resistant AES-ECB Cryptographic Cores prevent against the leakage of secret cryptographic key material through attacks wh...
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AES-ECB 1 Billion Trace DPA Resistant Crypto Accelerator
Rambus Crypto Accelerator AES-AE–Fast Hardware Cores offload compute intensive cryptographic algorithms in SoC’s CPU at 100x performance (when run at ...
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AES-ECB Accelerator
The EIP-32 AES Engines implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publ...
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AES-ECB-CBC-CFB-CTR 1 Billion Trace DPA Resistant Crypto Accelerator
Rambus DPA Resistant AES-FBC Cryptographic Accelerator Cores offload compute intensive cryptographic algorithms in SoC’s CPU at 100x performance (when...
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AES-ECB-CBC-CFB-CTR-GCM 1 Billion Trace DPA & Fault Injection Resistant Crypto Accelerator
Rambus DPA & Fault Injection Resistant AES-AE Cryptographic Cores prevent against the leakage of secret cryptographic key material through attacks whe...
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AES-ECB-CBC-CFB-CTR-GCM 1 Billion Trace DPA Resistant Crypto Accelerator
Rambus Crypto Accelerator AES-AE–Fast Hardware Cores offload compute intensive cryptographic algorithms in SoC’s CPU at 100x performance (when run at ...
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AES-ECB-CBC-CFB-OFB-CTR Crypto Accelerator
The EIP-36 AES Engines implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publ...
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AES-ECB-CBC-CFB-OFB-CTR-GCM-XTS-CCM Crypto Accelerator
The EIP-39 AES Accelerators implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS)...
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AES-GCM Multi-channel upto 2Tbps Crypto Accelerator
The EIP-63, high speed AES-GCM engine is a scalable high-performance, multi-channel cryptographic engine that offers AES-GCM operations as well as AES...
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AES-GCM Single-channel Crypto Accelerator
The EIP-61 is the IP for accelerating AES-GCM based cryptographic solutions. Designed for easy integration and very high performance the EIP-61 crypto...
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AES-GCM Single-channel Crypto Accelerator
The EIP-61 is the IP for accelerating AES-GCM based cryptographic solutions. Designed for easy integration and very high performance the EIP-61 crypto...
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AES-GCM-XTS Crypto Accelerator
The EIP-38 - AES/GCM/XTS/LRW Engines are specifically suited for next generation processors deployed in networking and storage appliances that need to...
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VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs
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VESA DisplayPort 1.4 Forward Error Correction (FEC) Receiver
The DisplayPort Forward Error Correction (FEC) Receiver IP core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPo...
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VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
The DisplayPort Forward Error Correction (FEC) Transmitter IP core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA Displa...
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VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
The DisplayPort Forward Error Correction (FEC) Transmitter IP core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA Displa...
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VESA DisplayPort 2.0 FEC RX
The DisplayPort Forward Error Correction (FEC) Receiver IP Core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPo...
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VESA DSC (Display Stream Compression) 1.2b Video Decoder
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VESA DSC (Display Stream Compression) 1.2b Video Encoder
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VESA DSC 1.2b Decoder IP Core for Xilinx FPGAs
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VESA DSC 1.2b Encoder for Xilinx FPGAs
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ChaCha20 Crypto Accelerator
The EIP-13 ChaCha engine implements the ChaCha20 algorithm, as specified by [ChaCha]. The accelerators include I/O registers and an encryption/decrypt...
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ChaCha20 DPA Resistant Crypto Accelerator
Rambus DPA Resistant Hardware Cores prevent against the leakage of secret cryptographic key material through attacks when integrated into an SoC or FP...
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Whirlpool Crypto Accelerator
Rambus DPA Resistant Hardware Cores prevent against the leakage of secret cryptographic key material through attacks when integrated into an SoC or FP...
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MIPI Testbench
Rambus MIPI Testbench from Rambus emulates a MIPI device enabling end-to-end simulation of a MIPI design. This includes the follow features: • Separ...
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FIPS 140-2 certified cryptographic software module
SafeZone FIPS cryptographic module is a compact and portable cryptographic library validated by NIST (certificate 3661; https://csrc.nist.gov/Project...
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FIPS Security Toolkit for OpenSSL
The Rambus FIPS Security Toolkit (formerly from Inside Secure) is a complete cryptographic security solution for IoT providing the tools required to s...
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Circuit Camouflage Technology
Rambus Circuit Camouflage Technology (formerly Inside Secure), also known as SecureMedia Library (SML), is an anti-reverse engineering and anti-clonin...
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Ultra Ethernet TSS Complete Layer with rates up to 1.6Tbps
The UET-TSS-IP-369 (EIP-369) is an inline, high-performance, multi-channel packet engine that provides the complete TSS layer, bypass/drop and basic c...
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Ultra Ethernet TSS Transform Engine with rates up to 1.6Tbps
The UET-TSS-IP-69 (EIP-69) is a high-performance, multi-channel transform engine that provides the complete TSS packet transformation (including KDF a...
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SM3 Crypto Accelerator
The EIP-52 SM3 Engine implements the SM3 hash algorithm. The accelerators include I/O registers, hash calculation cores, message padding logic, and da...
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SM4 Crypto Accelerator
The EIP-12 SM4 Engine implements the SM4 cipher block algorithm. The accelerator includes I/O registers, encryption and decryption cores. Designed for...