3101 0.0

PCIe 5.0 PHY IP for TSMC N5 The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s application...

3102 0.0

PCIe 5.0 Premium Controller with AXI bridge & Advanced HPC Features (Arm CCA) The complete silicon-proven DesignWare® IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Securit...

3103 0.0

PCIe 6.0 Controller EP/RP/DM/SW with AMBA bridge & HPC features, including Arm Confidential Compute Architecture The configurable and scalable Synopsys Controller IP for PCI Express® (PCIe®) 6.0 supports all required features of the PCI Express 6.0 specification...

3104 0.0

PCIe 6.0 Controller IP The Wolley PCI Express® (PCIe®) Controller IP is a highly configurable, performance-optimized core designed for ASIC and FPGA integration. Supporting ...

3105 0.0

PCIe 6.0 PHY for TSMC N6 The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interfac...

3106 0.0

PCIe 6.0 PHY in Samsung (SF2A) The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interfac...

3107 0.0

PCIe 6.0 PHY in TSMC (N3A) for Automotive The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interfac...

3108 0.0

PCIe 6.0 PHY IP for TSMC N3E The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interfac...

3109 0.0

PCIe 6.0 PHY IP for TSMC N4P The multi-channel Synopsys PHY IP for PCI Express (PCIe) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interface ...

3110 0.0

PCIe 6.0 PHY IP for TSMC N5 The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interfac...

3111 0.0

PCIe 6.0 PHY NCS IP for TSMC (N3E, N3P) The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interfac...

3112 0.0

PCIe 7.0 Controller (can be configured to support EP, RP, DM, or SW applications) The configurable and scalable Synopsys Controller IP for PCI Express® (PCIe®) 7.0 supports all required features of the PCI Express 7.0 specification,...

3113 0.0

PCIe 7.0 Integrity and Data Encryption (IDE) Security IP Module PCI Express is a ubiquitous interface for a wide variety of applications, from connecting accelerators and peripheral devices to data center servers t...

3114 0.0

PCIe 7.0 PHY for TSMC N5 The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across backplane, and c...

3115 0.0

PCIe 7.0 PHY in Samsung (SF4X) The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across backplane, and c...

3116 0.0

PCIe 7.0 PHY in TSMC (N7A, N5A, N3A) for Automotive The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across backplane, and c...

3117 0.0

UCIe Controller for Streaming Protocols Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The...

3118 0.0

UCIe PHY IP on TSMC N3P Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

3119 0.0

UCIe PHY on Samsung SF5A Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netwo...

3120 0.0

UCIe PHY on TSMC N3E Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netwo...

3121 0.0

UCIe-A PHY for Advanced Package (x64) in Samsung (SF2) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

3122 0.0

UCIe-A PHY for Advanced Package (x64) in Samsung (SF4X) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

3123 0.0

UCIe-A PHY for Advanced Package (x64) in TSMC (N5) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

3124 0.0

UCIE-A PHY, 5nm/4nm The InPsytech (IPT) UCIe-A PHY is a mass-production proven, state-of-the-art physical layer interface designed to provide exceptional performance and ...

3125 0.0

UCIE-A PHY, ADVANCED PACKAGE The InPsytech (IPT) UCIe-A PHY is a state-of-the-art physical layer interface, offering industry-leading power efficiency and proven in mass productio...

3126 0.0

UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC (N3P) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

3127 0.0

UCIe-S PHY for Standard Package (x16) for Automotive in TSMC (N5A) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

3128 0.0

UCIe-S PHY for Standard Package (x32) in TSMC (N3P) Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...

3129 0.0

CCIR 656 Decoder The Digital Blocks DB1840 CCIR 656 Decoder IP Core decodes an ITU-R BT.656 digital video uncompressed NTSC 720x486 (525/60 Video System) and PAL 720x5...

3130 0.0

CCIR 656 Encoder The Digital Blocks DB1830 CCIR 656 Encoder IP Core encodes 4:2:2 Y’CbCr component digital video with synchronization signals to conform to NTSC & PAL ...

3131 0.0

PCM to Class D Amplifier The AR35S13B is a high-performance digital Class D Amplifier IP for mono speaker playback application. The amplifier converts 16-24 bits digital PCM (...

3132 0.0

ACS-AIP-DPHY-40GF-Auto - MIPI D-PHY in GlobalFoundries 40nm Automotive Process Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...

3133 0.0

ACS-AIP-DPHY-40LP-RA - MIPI D-PHY TSMC 40LP Renesas- Automotive Grade Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...

3134 0.0

Active frequency doubler, designed for use in the LO Path after VCO to double up the LO frequency RFDBL04C is an active frequency doubler, designed for use in the LO Path after VCO to double up the LO frequency within the IC to feed in and drive th...

3135 0.0

Active frequency doubler, designed for use in the LO Path after VCO to double up the LO frequency RFDBL03C is an active frequency doubler, designed for use in the LO Path after VCO to double up the LO frequency within the IC to feed in and drive th...

3136 0.0

3D GPU compatible with OpenGL ES (3D Graphics API) and OpenCL (Computing API) DMP M3000 3D GPU IP Core adopts 3rd generation 3D graphics architecture Musashi and make remarkable progress in PPA (Power, Performance, Area) perform...

3137 0.0

3D GPU supporting OpenGL ES2.0 capability The DMP ant300 is the world’s smallest class 3D graphics IP core supporting OpenGL ES2.0 capability. It is the premiere solution for popular ASIC/ASSP...

3138 0.0

2D Graphics IP Core DMP K3000 2D GPU IP Core offers the most powerful rendering performance in the industry, with a minimum area solution. You will witness blazing font a...

3139 0.0

2D Graphics Rendering Engine Digital Blocks 2D Graphics Hardware Accelerator Verilog IP Cores consists of the DB9200AXI4, DB9200AXI, DB9200AHB, and DB9200AVLN. The DB9200 2D Graph...

3140 0.0

MD5 Hashing Core The es1005 hash fully implements the MD5 (Message Digest Algorithm RFC 1321). The core can be used for data authentication in digital broadband, wire...

3141 0.0

HDCP 2.0 Encryption Suite HDCP Suite consists of hardware and software components implementing the HDCP 2.0 protocol. The hardware components are fully synchronous and availabl...

3142 0.0

HDCP Encryption-Decryption Engine The Trilinear Technologies High-bandwidth Digital Content Protection (HDCP) Encryption-Decryption Engine IP core allows system designers to accelerate...

3143 0.0

GDDR6 Memory PHY for TSMC N5P Designed for high performance and low latency in AI/ML, graphics and networking The latest, the Denali PHY IP for GDDR6, is comprised of architectura...

3144 0.0

GDDR6 Memory PHY for TSMC N7 Designed for high performance and low latency in AI/ML, graphics and networking The latest, the Denali PHY IP for GDDR6, is comprised of architectura...

3145 0.0

GDDR6 PHY for TSMC N6 High-performance IP for graphics, AI/ML, and automotive products The latest, the Denali PHY IP for GDDR6, is comprised of architectural improvements ...

3146 0.0

GDDR7 Memory PHY for TSMC N3P High performance for graphics, AI, and automotive products The Cadence IP solution for GDDR7 consists of high-performance hardened PHY, serving hig...

3147 0.0

GDDR7 Memory PHY for TSMC N4P High performance for graphics, AI, and automotive products The Cadence IP solution for GDDR7 consists of high-performance hardened PHY, serving high-...

3148 0.0

GDDR7 Memory PHY for TSMC N5P High performance for graphics, AI, and automotive products The Cadence IP solution for GDDR7 consists of high-performance hardened PHY, serving high-...

3149 0.0

SDIO HOST VMM based Verification IP The Secure Digital Input Output (SDIO) interface is a card interface defined to connect a SD Host Controller with four different types of cards, namel...

3150 0.0

3DIO PHY IP for TSMC N5 Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...