Sansa Security, Inc. (now ARM Holdings) IP Cores

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Complete datasheets for Sansa Security, Inc. (now ARM Holdings) IP Core products
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1801

1.0

UMC L180G 180nm Spread Spectrum PLL - 100MHz-500MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1802

1.0

UMC L180G 180nm Spread Spectrum PLL - 200MHz-1000MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1803

1.0

UMC L180G 180nm Spread Spectrum PLL - 50MHz-250MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1804

1.0

UMC L55SP 55nm Clock Generator PLL - 130MHz-650MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1805

1.0

UMC L55SP 55nm Clock Generator PLL - 260MHz-1300MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1806

1.0

UMC L55SP 55nm Clock Generator PLL - 520MHz-2600MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1807

1.0

UMC L55SP 55nm DDR DLL - 150MHz-750MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1808

1.0

UMC L55SP 55nm DDR DLL - 200MHz-1000MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1809

1.0

UMC L55SP 55nm DDR DLL - 316MHz-1580MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1810

1.0

UMC L55SP 55nm Deskew PLL - 130MHz-650MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1811

1.0

UMC L55SP 55nm Deskew PLL - 260MHz-1300MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1812

1.0

UMC L55SP 55nm Deskew PLL - 520MHz-2600MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1813

1.0

UMC L55SP 55nm Spread Spectrum PLL - 130MHz-650MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1814

1.0

UMC L55SP 55nm Spread Spectrum PLL - 260MHz-1300MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1815

1.0

UMC L55SP 55nm Spread Spectrum PLL - 520MHz-2600MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1816

1.0

UMC L65LL 65nm Clock Generator PLL - 120MHz-600MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1817

1.0

UMC L65LL 65nm Clock Generator PLL - 240MHz-1200MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1818

1.0

UMC L65LL 65nm Clock Generator PLL - 60MHz-300MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1819

1.0

UMC L65LL 65nm DDR DLL - 104MHz-520MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1820

1.0

UMC L65LL 65nm DDR DLL - 164MHz-820MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1821

1.0

UMC L65LL 65nm DDR DLL - 78MHz-390MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1822

1.0

UMC L65LL 65nm Deskew PLL - 120MHz-600MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1823

1.0

UMC L65LL 65nm Deskew PLL - 240MHz-1200MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1824

1.0

UMC L65LL 65nm Deskew PLL - 60MHz-300MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1825

1.0

UMC L65LL 65nm Spread Spectrum PLL - 120MHz-600MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1826

1.0

UMC L65LL 65nm Spread Spectrum PLL - 240MHz-1200MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1827

1.0

UMC L65LL 65nm Spread Spectrum PLL - 60MHz-300MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1828

1.0

UMC L65SP 65nm Clock Generator PLL - 130MHz-650MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1829

1.0

UMC L65SP 65nm Clock Generator PLL - 260MHz-1300MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1830

1.0

UMC L65SP 65nm Clock Generator PLL - 520MHz-2600MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1831

1.0

UMC L65SP 65nm DDR DLL - 150MHz-750MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1832

1.0

UMC L65SP 65nm DDR DLL - 200MHz-1000MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1833

1.0

UMC L65SP 65nm DDR DLL - 316MHz-1580MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1834

1.0

UMC L65SP 65nm Deskew PLL - 130MHz-650MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1835

1.0

UMC L65SP 65nm Deskew PLL - 260MHz-1300MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1836

1.0

UMC L65SP 65nm Deskew PLL - 520MHz-2600MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1837

1.0

UMC L65SP 65nm Spread Spectrum PLL - 130MHz-650MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1838

1.0

UMC L65SP 65nm Spread Spectrum PLL - 260MHz-1300MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1839

1.0

UMC L65SP 65nm Spread Spectrum PLL - 520MHz-2600MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1840

1.0

UMC L80G 80nm Clock Generator PLL - 120MHz-600MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1841

1.0

UMC L80G 80nm Clock Generator PLL - 240MHz-1200MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1842

1.0

UMC L80G 80nm Clock Generator PLL - 480MHz-2400MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1843

1.0

UMC L80G 80nm DDR DLL - 129MHz-645MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1844

1.0

UMC L80G 80nm DDR DLL - 172MHz-860MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1845

1.0

UMC L80G 80nm Deskew PLL - 120MHz-600MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1846

1.0

UMC L80G 80nm Deskew PLL - 240MHz-1200MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1847

1.0

UMC L80G 80nm Deskew PLL - 480MHz-2400MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1848

1.0

UMC L80G 80nm Spread Spectrum PLL - 120MHz-600MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1849

1.0

UMC L80G 80nm Spread Spectrum PLL - 240MHz-1200MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1850

1.0

UMC L80G 80nm Spread Spectrum PLL - 480MHz-2400MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

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