Design & Reuse
4641 IP
901
0.0
VeriSilicon 802.15.4g(WiSUN) RF IP
LIGHT is a RF transceiver designed for 433-510MHz applications which can transmit up to +23dBm peak power with integrated power amplifier and on-chip ...
902
0.0
VeriSilicon Bluetooth Dual-Mode (BTDM) RF IP
GF22FDXV18_BTDM_03 is a 2.4GHz ISM Band RF Transceiver IP which is designed for Bluetooth dual mode applications. It is compliant with the Bluetooth s...
903
0.0
VeriSilicon Bluetooth Low Energy (BLE) 5.3 BB IP
The BLE Baseband Controller is a digital IP implementing all functions of BLE modulation and link layer defined in Bluetooth Core Specification 5.3. I...
904
0.0
VeriSilicon IoT Platform
IoT forms a vast network of devices that sense, communicate or interact with each other. These connected devices are found in various end markets like...
905
0.0
VeriSilicon LTE Cat1.bis RF IP
TSMC28V18_LTE1T1R_RF IP is a radio transceiver macro which is designed for the 4G LTE Cat-1.bis UE working in cellular wireless communication. It comp...
906
0.0
VeriSilicon NB-IoT BB IP
The NB-IoT BB IP is a digital IP designed to implement complete physical layer functions of Cat NB1 and NB2 defined in 3GPP standards. It provides NB-...
907
0.0
Neural Network Processor for Intelligent Vision, Voice, Natural Language Processing
Efficient and Versatile Computer Vision, Image, Voice, Natural Language, Neural Network Processor...
908
0.0
High Image Quality Super Resolution IP
VeriSilicon's SR2000 series IPs are silicon-proven, super resolution designs for smart display. Currently consisting of SR2000L, SR2000, and SR2000H, ...
909
0.0
High-performance and low-power display processing IP-DC9x00
VeriSilicon's Vivante DC9x00 series IPs are high-performance, low-power display processing IPs that deliver exceptional visual effects in different ap...
910
0.0
MIPI CDPHY TX & RX V2.1/V3.0
This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v2.1 and D-PHY v3.0”, which consists of Bi-directional 1-Clock and 4-Data lanes. It c...
911
0.0
MIPI CDPHY TX & RX V2.1/V3.0
This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v2.1 and D-PHY v3.0”, which consists of Bi-directional 1-Clock and 4-Data lanes. It c...
912
0.0
Display unit and graphics accelerator for IoT and wearables
...
913
0.0
Embedded Vivante GPU, Vision, and IoT cores
Our impressive range of scalable, licensable Vivante GPU cores addresses the rapidly advancing expectations of the semiconductor marketplace from smal...
914
0.0
Interface Controller - PHY IP
The UCIE PHY IP is a market leading, extremely low-power, low-latency interface IP for very high bandwidth connections between two dies that are on th...
915
0.0
Comprehensive, High Throughput Pixel Operation IP
The PC820 pixel processor is an IP which provides pixel processing functions such as cropping, color space conversion (CSC), alpha blending, 3D LUT, a...
916
0.0
USB3.2 PHY on Samsung S8LPU
This IP is a USB 3.2 Gen2x2 PHY IP which provides a complete range of USB 3.2 Gen2 host and peripheral applications up to 20Gbps. The USB 3.2 Gen2x2 I...
917
0.0
USB3.2 PHY on Samsung SF4X
This IP is a USB 3.2 Gen2x2 PHY IP which provides a complete range of USB 3.2 Gen2 host and peripheral applications up to 20Gbps. The USB 3.2 Gen2x2 I...
918
0.0
ZSP-USB-JTAG Emulator
The ZSP-USB-JTAG emulator probe enables efficient and productive embedded software debugging. This compact and portable probe is powered by the USB po...
919
0.0
eUSB2 PHY on Samsung SF4X
The Embedded USB 2.0 PHY is a High speed System-on-Chip (SoC) integrated transceiver IP in advanced process that implements the Intel® UTMI standard. ...
920
0.0
ZView IDE - ZSP Development Environment
The ZView Integrated Development Environment (IDE) features a debugger as part of the Eclipse software development environment. Eclipse is an open, in...
921
130.0
LPDDR6, LPDDR5X Combo PHY & Controller
INNOSILICON™ introduces its LPDDR6/5X PHY and Controller IP, purpose-built for the AI era’s high-performance chip design needs. This solution is fully...
922
100.0
1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
eTopus designs ultra-high speed mixed-signal semiconductor IP solutions for high-performance computing and data center applications. Our 1-56/112Gbps ...
923
100.0
400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
...
924
100.0
56G Serdes in 7nm bundled with PCie Gen 5 controller IP
New IP for value conscious designers....
925
100.0
PCIe 5.0 PHY & Controller
The Innosilicon Gen1/2/3/4/5 PCI Express Controller provides a PCI Express Root Complex (RC) and Endpoint (EP) application. It’s a high performance, h...
926
100.0
PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
Multiprotocol low latency, low power SERDES IP....
927
100.0
The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.
SuperFlash® is SST’s patented and proprietary NOR flash technology. With 80B+ devices shipped, SuperFlash is the non-volatile memory of choice for emb...
928
100.0
Complete USB Type-C Power Delivery PHY, RTL, and Software
The OTI9108 is a complete single transceiver front end for data USB PD Type-C (baseband) communications. It has a register interface which, with an MP...
929
100.0
LPDDR5X, LPDDR5, LPDDR4X, LPDDR4 Combo PHY & Controller
The INNOSILICON™ LPDDR IP includes a LPDDR5X/5/4X/4 Combo PHY and controller. It is fully compliant with the JEDEC standard. Optimized for low-power a...
930
80.0
GDDR7 PHY & Controller
The INNOSILICON™ GDDR7 PHY is fully compliant with the JEDEC GDDR7 standard, supporting data rates of up to 32 Gbps in PAM3 mode. In PAM3 mode, each b...
931
70.0
DDR4/3, LPDDR5x/5/4x/4 Memory Controller IP
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
932
70.0
LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
933
70.0
LPDDR5X/5/4X/4 Memory Controller IP
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
934
60.0
UCIe Chiplet PHY & Controller
INNOSILICON™ UCIe Chiplet IP offers a customizable solution for seamless, low-latency data transfer between silicon dies and chips, enabling heterogen...
935
60.0
IGAHBMV03A, TSMC CLN16FFC HBM PHY with CoWoS technology
IGAHBMV03A, TSMC CLN16FFC HBM PHY with CoWoS technology...
936
50.0
512x8 Bits OTP (One-Time Programmable) IP, TSM- 12FFC 0.8V/1.8V Process
The ATO00512X8TS012FFC8EA is organized as 512 bits by 8 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in 12nmFFC stand...
937
50.0
High Bandwidth Out-of-Order RISC-V CPU IP Core
...
938
50.0
High Bandwidth Out-of-Order RISC-V CPU IP Core
...
939
50.0
LPDDR5/4x/4 combo PHY on 14nm, 12nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
940
46.0
32Gbps, 31 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter
This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 31 order, up to 32Gbps. Error count is accurate: no double counts or omissions reg...
941
46.0
32Gbps, 7/15 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter
This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 7 or 15 order, up to 32Gbps. Error count is accurate: no double counts or omission...
942
46.0
32Gbps, 7/15/31 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter
This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 7, 15 or 31 order, up to 32Gbps. Error count is accurate: no double counts or omis...
943
40.0
LPDDR5X/5/4X/4 combo PHY at 7nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
944
40.0
LPDDR5X/5/4X/4 PHY for 16nm
The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...
945
40.0
LPDDR5X/5/4X/4 PHY IP for 12nm
The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...
946
30.0
4-/8-bit mixed-precision NPU IP
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
947
30.0
UCIe Die-to-Die Chiplet Controller
Introducing OPENEDGES’ Universal Chiplet Interconnect Express (UCIe) Controller IP, OUC, designed to transform the semiconductor landscape with innova...
948
30.0
UFS Host Controller 4.1 IP
The UFS Host Controller Interface (UFSHCI) is a high-performance interface that connects to UniPro and M-PHY IP in mobile platforms. It provides comma...
949
30.0
High speed NoC (Network On-Chip) Interconnect IP
OPENEDGES is the only total memory system IP company providing both memory controller and on-chip interconnect. OIC is the ORBIT high-speed On-chip In...
950
30.0
Highly scalable inference NPU IP for next-gen AI applications
OPENEDGES, the total memory subsystem IP provider, introduces ENLIGHT Pro, a state-of-the-art inference neural processing unit (NPU) IP that outperfor...