Design & Reuse
Catalog of SIP Cores
System on Chip design resources
614 IP
501
0.0
Simulation VIP for MIPI D-PHY, C-PHY and A-PHY
Cadence provides a mature and comprehensive Verification IP (VIP) for the D-PHY/C-PHY/A-PHY, which is part of the MIPI family. Incorporating the lates...
502
0.0
Simulation VIP for MIPI DBI
Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for MIPI® DBI-2sm Protocols provides a complete...
503
0.0
Simulation VIP for MIPI DPI
Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for MIPI® DPIsm Protocols provides a complete b...
504
0.0
Simulation VIP for MIPI DSI-2
In production since 2008 on dozens of production designs....
505
0.0
Simulation VIP for MIPI I3C
In production since 2015 on dozens of production design....
506
0.0
Simulation VIP for MIPI M-PHY
In production since 2011 on dozens of production designs....
507
0.0
Simulation VIP for MIPI RFFE
Cadence provides a mature and comprehensive Verification IP (VIP) for the MIPI® RF Front-End Control Interface (RFFEsm) protocol. Incorporating the la...
508
0.0
Simulation VIP for MIPI SLIMbus
Cadence provides a mature and comprehensive Verification IP (VIP) for the SLIMbus protocol, which is part of the MIPI family. Incorporating the latest...
509
0.0
Simulation VIP for MIPI SoundWire
In production since 2015 on dozens of production designs....
510
0.0
Simulation VIP for MIPI SoundWire-I3S
Best-in-class MIPI® SoundWire-I3Ssm (SWI3S) Verification IP for your IP, SoC, and system-level design testing....
511
0.0
Simulation VIP for MIPI SPMI
Cadence provides a mature and comprehensive Verification IP (VIP) for the MIPI® SPMIsm (System Power Management Interface) protocol. Incorporating the...
512
0.0
Simulation VIP for MIPI UniPro
In production since 2011 on dozens of production designs....
513
0.0
Simulation VIP for NVMe
The Cadence® Verification IP (VIP) for NVMe is part of Cadence's storage interface VIP portfolio. It provides a mature and highly capable compliance v...
514
0.0
Simulation VIP for OCP
In production since 2011 for dozens of designs....
515
0.0
Simulation VIP for OctaRam
In production since 2018 for many production designs....
516
0.0
Simulation VIP for ONFi
In production since 2011 for dozens of production designs....
517
0.0
Simulation VIP for OSPI NOR
In production since 2012 for dozens of designs....
518
0.0
Simulation VIP for PCIe
Used by all leading PCIe, IP, and SoC design verification teams for all generations....
519
0.0
Simulation VIP for PIPE PHY
The Cadence® PIPE PHY Verification IP (VIP) provides a mature, highly capable verification solution for the PHY layer of complex protocols such as PCI...
520
0.0
Simulation VIP for PLB
In production since 2011....
521
0.0
Simulation VIP for PMBus
Incorporating the latest protocol updates, the Cadence® Verification IP (VIP) for PMBus provides a complete bus functional model (BFM), integrated aut...
522
0.0
Simulation VIP for Q-SPI
In production since 2018 for many production designs....
523
0.0
Simulation VIP for SAS
The Cadence® Verification IP (VIP) for SAS is part of Cadence’s broad storage interface verification IP (VIP) portfolio. Serial Attached SCSI (SAS) ha...
524
0.0
Simulation VIP for SD CARD and SDIO
In production since 2012 for many production designs....
525
0.0
Simulation VIP for SMBus
Incorporating the latest protocol updates, the Cadence® Verification IP (VIP) for SMBus provides a complete bus functional model (BFM), integrated aut...
526
0.0
Simulation VIP for SPDIF
Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for the SPDIF protocol provides a complete bus ...
527
0.0
Simulation VIP for SPI
This Cadence® Verification IP (VIP) provides support for the SPI protocol. The SPI VIP provides a complete bus functional model (BFM) and integrated a...
528
0.0
Simulation VIP for SPI NAND
In production since 2016 for many production designs....
529
0.0
Simulation VIP for TileLink
This Cadence® Verification IP (VIP) provides support for the TileLink specification. It provides a highly capable compliance verification solution sim...
530
0.0
Simulation VIP for Toggle NAND
In production since 2011 for many production designs....
531
0.0
Simulation VIP for UART
Best-in-class UART Verification IP for your IP, SoC and system-level design testing. In production since 2014 on dozens of production designs....
532
0.0
Simulation VIP for UCIE
Best-in-class UCIe Verification IP for your IP, SoC, and system-level design testing....
533
0.0
Simulation VIP for UCIE
Best-in-Class UCIe Verification IP for your IP, SoC, and System-Level Design Testing The Cadence Verification IP (VIP) for Universal Chiplet Interconn...
534
0.0
Simulation VIP for UFS
In production since 2012 on multiple production designs....
535
0.0
Simulation VIP for USB
The Cadence® Verification IP (VIP) for USB is a complete VIP solution for the Universal Serial Bus Revision 3.2 Specification and errata. It provides ...
536
0.0
Simulation VIP for USB4
Used by all top market leaders semiconductor companies....
537
0.0
Simulation VIP for xSPI
xSPI in production since 2019 for many production designs....
538
0.0
Aion Silicon - Custom ASIC or SoC Design Services
Aion Silicon (formerly Sondrel) can create a custom ASIC to take your product line into its next phase of development or create a flexible System on C...
539
0.0
Zipcores Electronic Systems Engineering - Custom Design Services
At Zipcores we are experts in all matters relating to the design, implementation and test of digital circuits on FPGA, SoC and ASIC devices. To this ...
540
0.0
RISC - DRV32IMZicsr - 32-bit RISC-V CPU with M, Zicsr extensions, and External Debug support
The DRV32IMZicsr is a 32-bit RISC-V CPU with M, Zicsr extensions, and External Debug support. The Core belongs to the latest DCD’s DRVX Core Family...
541
0.0
RISC - DRV64IMZicsr - 64-bit RISC-V CPU with M, Zicsr extensions and External Debug support
The DRV64IMZicsr is a 64-bit RISC-V CPU with M, Zicsr extensions and External Debug support. As a part of the DRVX Core Family this unique CPU offers:...
542
0.0
VisualSim AI Evaluator
VisualSim AI Evaluator is an AI evaluator that combines analog, digital, power and network modeling to select the right architecture for the accelerat...
543
0.0
VisualSim Artificial Intelligence (AI)-driven Processor Generator
VisualSim Processor Generator is a revolutionary and extremely intelligent library. The library contains the generators and a large set of pre-define...
544
0.0
VisualSim Explorer
VisualSim Explorer is a Web Server that enables models to be embedded in documents for viewing, simulation and analysis from within a Web Browser with...
545
0.0
Bitec Spain SL - Consultancy and design services
BITEC was founded in 2002 with the aim of providing a high quality technology advice to customers worldwide. Bitec is headquartered in Marbella, Spain...
546
0.0
BitFlex-SPB-A7 - advanced hardware design platform
The BitFlex-SPB-A7, an advanced hardware design platform centered around the powerful Xilinx Artix-7 FPGA. This cutting-edge board boasts high-perform...
547
0.0
BitSim AB - Consulting and Design services
What functionality do you want and what are the market requirements? This is always the starting point of all our development projects. Our team of e...
548
0.0
Global Unichip Corporation - SoC Design Services
GUC has been delivering SoC design services on 0.5um to 16nm technology. GUC chip implementation solution resolves the challenges of multi-hundred-mil...
549
0.0
VLSI Plus - ISP Design Services and Engineering Services
VLSI Plus team of image processing professional, experienced in the definition and efficient VLSI implementation of high image quality ISP (Image Si...
550
0.0
DMA - DDMA - Direct Memory Access Controller
The DDMA is a four-channel Direct Memory Access Controller. Its purpose is to transfer data between memories and peripherals to reduce CPU utilization...