Design & Reuse
3828 IP
501
3.0
SNOW 3G Encryption Core
The SNOW3G1 core implements SNOW 3G stream cipher in compliance with the ETSI SAGE specification version 1.1. It produces the keystream that consists ...
502
3.0
Complete measurement analog front end (AFE) IP for single phase power metering in TSMC 40uLPeF
METRO-PM-MFE-mono.11-HD-IVT_TSMC_40_uLPeF is a Mixed-signal (analog and digital) Virtual Component in TSMC 40uLPeF. It is comprised of a high resoluti...
503
3.0
Complete measurement analog front end (AFE) IP for three-phase power metering in SMIC 40LL-RF
METRO-PM-JADE-3P.11-HD_SMIC_40_LL-RF is a Mixed signal (analog and digital) Virtual Component in SMIC 40LL-RF which offers a complete analog front-end...
504
3.0
Complete measurement analog front end (AFE) IP for three-phase power metering in TSMC 40uLPeF
METRO-PM-JADE-3P.11-HD_TSMC_40_uLPeF is a Mixed-signal (analog and digital) Virtual Component in TSMC 40uLPeF. It is comprised of a high resolution Mi...
505
3.0
complete measurement subsystem IP for single phase power meteringi in HHGrace 130eF
Metro-Jade-PM-mono-10-HD-OV_HHGrace_130_eF is a Mixed signal (analog and digital) Virtual Component in HHGrace 130eF which offers a complete analog fr...
506
3.0
FortifyIQ High-Performance Hybrid Classical and Post-Quantum High-assurance (SCA/DPA/FIA resistant) Cryptography IP Core (ECC/RSA, ML-KEM, ML-DSA)
FortifyIQ’s High-Performance Hybrid Cryptography IP core delivers accelerated support for both classical (RSA, ECC) and post-quantum (ML-KEM, ML-DSA) ...
507
3.0
FortifyIQ Hybrid Classical and Post-Quantum High-assurance (SCA/DPA/FIA resistant) Cryptography IP Core (ECC/RSA, ML-KEM, ML-DSA)
FortifyIQ’s Hybrid Cryptography IP core combines traditional asymmetric algorithms, such as RSA and ECC, with post-quantum standards including ML-KEM ...
508
3.0
FortifyIQ's Compact DPA and FIA Hardened Post-Quantum ML-KEM IP Core for Resource-Constrained Devices (SCA/DPA/FIA resistant)
As quantum computing threatens traditional public-key cryptography, resource-constrained devices must adopt quantum-resistant algorithms without compr...
509
3.0
LPDDR2/3/4/4x IP combo solution with high performance and low power
With sophisticated architecture and advanced technology, this LPDDR2/3/4/4x IP combo solution with high performance and low power. In 12~28nm CMOS pro...
510
3.0
True Random and Pseudorandom Number Generator
The true random generator core implements true random number generation. The core passes the American NIST Special Publication 800-22 and Diehard Rand...
511
3.0
LRW-AES Core
LRW3 implements the NIST standard AES cipher in the LRW mode for encryption and decryption. The LRW3 family of cores covers a wide range of area / thr...
512
3.0
LRW-AES Core
Implementation of the older drafts standard IEEE P1619 required the NIST standard AES cipher in the LRW mode for encryption (AES-LRW). Note that the n...
513
3.0
LRW-AES Core
Implementation of the new encrypted shared storage media standard IEEE P1619 with AES cipher in the LRW mode....
514
3.0
Cryptographically Secure Pseudo Random number Generator IP Core
The PRNG1 core implements a cryptographically secure pseudo-random number generator per NIST publication SP800-90. Basic core is small (6,500 gates)...
515
3.0
RSA Public Key Exponentiation Accelerator
Rivest-Shamir-Adelman (RSA) is a public-key cryptographic technology that uses the mathematics of so called “finite field exponentiation”. The opera...
516
3.0
USB 2.0 (LS, FS & HS) On-The-Go IP Core
A 'Dual-Role' USB On-The-Go IP Core that operates as both an USB peripheral or as an USB OTG host in a point-to-point communications with another USB ...
517
3.0
SSL/TLS Processor IP Core with an AXI Bus Interface
The SSL1 core implements SSL and/or TLS frameworks with a configurable variety of cipher suites. SSL1-AXI has a “lookaside” interface to the rest of...
518
3.0
XTS-AES IEEE P1619 Core Families
XTS2 and XTS3 (formerly known as XEX2 and XEX3) implement the NIST standard AES cipher in the XEX/XTS mode for encryption and decryption. The XTS3 fa...
519
2.5
FAT32 IP Soft Core for NVMe
FAT32 IP Soft Core for NVMe...
520
2.5
SATA 3 HOST IP on ARRIA 10 FPGA
The LDS-SATA3-HOST-A10GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Match FIFO on a INTEL ARRIA 10 GX FPGA. The L...
521
2.5
LDS SATA RECORDER IP ON ARTIX 7
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522
2.5
Xilinx Kintex 7 NVME HOST IP
The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD....
523
2.5
Xilinx Ultra Scale NVME Host IP
The LDS NVME HOST K7U IP is one of the most flexible NVME HOST IP in the market. It has been done for beginners and expert in NVMe to drive NVMe PC...
524
2.5
Xilinx Ultra Scale Plus SATA HOST IP
The LDS_SATA3_HOST_GTHE4 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Ultra Scale Plus GTHE4 FPGA. The LDS_SATA3_...
525
2.5
Xilinx ZYNQ NVME HOST IP
The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD....
526
2.2581
2 separated LDO blocks IP ISTS_LDO2CH_S40V33
The ISTS_LDO2CH_S40V33 IP includes 2 separated LDO blocks to generate the power for PLL and 2.5V analog power application....
527
2.2581
Very low power IP with BOR/POR features embedded
The IST-POR02 IP is a very low power IP with BOR/POR features embedded. It detects the voltage level of core power DVDD and IO power AVDD. When AVDD r...
528
2.2581
Very low power IP with VDT/POR features embedded
The IST-POR05 IP is a very low power IP with VDT/POR features embedded. It detects the voltage level of IO power AVDD and core power. When AVDD rises ...
529
2.2581
Always on LDO IP IST-LDO33T15
The IST-LDO33T15 IP is a always on LDO to generate the power for Fuse, PLL, etc. application....
530
2.0
MAC Privacy Protection IP
The MAC Privacy Protection IP is a fully compliant solution that provides Ethernet Layer 2 Security for port and data privacy as standardized in IEEE ...
531
2.0
MIPI A-PHY Verification IP
MIPI A-PHY v1.0 is a physical layer communication protocol designed for automotive applications, including driver assistance, autonomous driving, and ...
532
2.0
Graphics Processor Overlay IP Core
The GPU_OVERLAY IP Core (Figure 1) is a highly versatile on-screen display processor that allows high-quality anti-aliased bitmap graphics and text to...
533
1.0
3.6Kbit EEPROM IP with configuration 28p8w16bit
GF130_EEPROM_01 is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 3.6Kbit, which is organized as 28 pages of 8...
534
1.0
10 Gigabit Ethernet XGMAC IP
Arasan’s 10 Gigabit Ethernet Media Access Controller (XGMAC) IP is compliant with the Ethernet IEEE 802.3-2008 standard and provides an interface betw...
535
1.0
1024-bit EEPROM IP with configuration 32p2w16bit
The block is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 1024 bits (16(bit per word) x 2(word per page) x 3...
536
1.0
16550D High Speed UART IP core - Universal Aysynchronous Receive/Transmit
Arasan 16550D High Speed UART IP core is a 16550-compliant Universal Asynchronous Receiver/Transmitter (UART) with FIFO or expanded FIFO. The UART...
537
1.0
36Kbyte EEPROM IP with configuration 288p32w32bit
The block is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 36Kbyte (32(bit per word) x 32(words per page) x 2...
538
1.0
36Kbyte EEPROM IP with configuration 288p32w32bit and oscillator
130GF_EEPROM_07 is a nonvolatile electrically erasable programmable read-only memory with volume 36Kbyte (32(bit per word) x 32(words per page) x 288(...
539
1.0
SATA HOST Synchronous IP
The LDS SATA HOST XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST XV5 IP is com...
540
1.0
PCIe 2.0 End Point IP Core - PCIe with FIFO Interface
The Arasan PCI Express End Point is a high-speed, high-performance, and lowpowerIP core that is fully compliant to the PCI Express Specification 1.1 a...
541
1.0
2D Compostion Processing IP
Vivancte 2D GPU processors provide high performance multi-surface composition which take all visual components of a screen, and processes and combines...
542
1.0
2D Compostion Processing IP
Vivancte 2D GPU processors provide high performance multi-surface composition which take all visual components of a screen, and processes and combines...
543
1.0
2D Compostion Processing IP
Vivancte 2D GPU processors provide high performance multi-surface composition which take all visual components of a screen, and processes and combines...
544
1.0
2D Compostion Processing IP
Vivancte 2D GPU processors provide high performance multi-surface composition which take all visual components of a screen, and processes and combines...
545
1.0
HDMI1.4 Transmitter IP
Innosilicon HDMI TX IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with HDMI...
546
1.0
VeriSilicon 400MHz 802.15.4g RF IP
LIGHT is a RF IP supporting general modulation modes on 433MHz~510MHz band. The IP is designed to support 3.3V operation voltage with SMIC 55nm proces...
547
1.0
VeriSilicon 802.11ah RF IP
802.11ah RF IP is a complete radio system for signal transmission and reception over wireless channels on the 863-928 MHz ISM frequency band. Its fun...
548
1.0
VeriSilicon Bluetooth Dual-Mode (BTDM) RF IP
Dual-mode Bluetooth RF IP is s a 2.4GHz ISM Band RF Transceiver IP which is designed for Bluetooth dual mode applications. It is compliant with the Bl...
549
1.0
VeriSilicon Bluetooth Low Energy (BLE) 5.3 RF IP
S55LLRFV25_BLE_04 is a 2.4GHz ISM band RF Transceiver IP which is designed for Bluetooth Smart applications. It is compliant with the Bluetooth Low En...
550
1.0
VeriSilicon Bluetooth Low Energy (BLE) 6 RF IP
This GF22FDX BLE RF IP is a 2.4GHz ISM Band RF Transceiver IP which is designed with GlobalFoundries FDX22 process for low-power Bluetooth application...