Design & Reuse
3828 IP
251
10.0
SD 4.1 SDIO 4.1 Host Controller IP
The SD 4.1/SDIO 4.1 IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports two key memory card I/O technologies:...
252
10.0
GDDR6 PHY IP for 12nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
253
10.0
Secure-IC's Securyzr™ Inline Decrypter IP Core
The Inline Decrypter IP Core enables on-the-fly execution of encrypted code from Flash. It is often used to protect the source code from decompiling o...
254
10.0
VESA DSC Encoder and Decoder IP Solutions
Synopsys VESA Display Stream Compression (DSC) Encoder and Decoder IP provides a video compression solution for up to 10K ultra-high-definition displa...
255
10.0
JESD204D - Succesfully Taped out, Silicon Agnostic IP core
The JESD204D Controller IP is based on the recently released D revision of the JEDEC standard for Serial Interface for Data Converters. The JESD204D I...
256
10.0
DesignWare Library contains the essential infrastructure IP for design and verification
The DesignWare Library contains the essential infrastructure IP for design and verification including datapath components, AMBA On-Chip Bus and microc...
257
10.0
UFS Host Controller IP
Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processors, baseband processor...
258
10.0
Die-to-Die Controller IP
The Synopsys Die-to-Die Controller IP, optimized for latency, bandwidth, power and area, enables efficient inter-die connectivity in server, AI accele...
259
10.0
Digital Physical Unclonable Function (PUF) IP
Our Digital PUF IP is a digital version of our quantum-based PUF IP (see QDID). The Logic-based Digital PUF IP is a strong hardware root-of-trust for ...
260
10.0
MIPI DSI-2 Transmitter Interface IP
MIPI DSI-2 (Display Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile dev...
261
10.0
MIPI I3C Controller and Target fully featured IP solution
The MIPI I3C Controller IP is a highly optimized and technology-agnostic implementation of the MIPI I3C v.1.1.1 standard targeting both ASIC and F...
262
10.0
Direct Memory Access DMA Controller IP Core
The DMA_CTRL core implements a low-power, single-channel Direct Memory Access (DMA) controller that is used to transfer data across a bus to and from ...
263
10.0
Visibility Improver IP
“LucidEye” improves the visibility of unclear images such as those deteriorated due to weather conditions (snow, haze, or fog), and dark images due t...
264
10.0
KiviHash-SHA-3 Secure Hash Algorithm (SHA-3) IP Core
The KiviHash-SHA-3 (secure hash algorithms) is a hardware accelerator for cryptographic hashing functions. It is an area efficient and high throughput...
265
10.0
4Kx16 Bits OTP (One-Time Programmable) IP, UM- 110 nm 1.2V/3.3V L110AE Process
The AT4K16U110MAE0DA is organized as a 4K-bits by 16 one-time programmable memory. This is a kind of non-volatile memory fabricated in UM- L110AE proc...
266
10.0
4Kx32 Bits OTP (One-Time Programmable) IP, TSM- 40nm ULP 1.1V/2.5V Process
The AT4K32T40ULP7ZC is organized as 4K-bits by 32 one-time programmable (OTP). This is a type of non-volatile memory fabricated in TSM- 40nm ULP stand...
267
10.0
4Kx8 Bits OTP (One-Time Programmable) IP, GLOBA-FOUNDR---® 22nm FDX 0.8V/1.8V Process
The AT4K8G22FDX0AA is organized as a 4K-bits by 8 one-time programmable memory. This is a kind of non-volatile memory fabricated in GLOBA-FOUNDR---® ...
268
10.0
8Kx8 Bits OTP (One-Time Programmable) IP, VI- 0.15µm 1.8V/5V BCD GIII Process
The AT8K8V150BCD0DB is organized as an 8K-bit by 8 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in VI- 0.15μm BCD GII...
269
10.0
Ultra High-Performance AES-GCM/CTR IP
The proliferation and expansion of connected devices, connectivity infrastructure, cloud computing, and artificial intelligence is driving for increas...
270
10.0
UniPro 1.6 Host/Device IP
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
271
10.0
UniPro 1.8 Host/Device IP
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
272
10.0
UniPro 1.8 Host/Device IP
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
273
10.0
UniPro Controller 2.0 IP (host / device)
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
274
10.0
FortifyIQ High-Performance Quantum-Ready CryptoBox IP Core (AES, HMAC-SHA2, RSA/ECC, PQC) SCA/DPA/FIA-Resistant)
FortifyIQ’s High-Performance Hybrid Crypto Box IP core delivers maximum cryptographic throughput by combining classical asymmetric (RSA, ECC), symmetr...
275
10.0
FortifyIQ's Compact Crypto Box IP Core for Resource-Constrained Devices (AES, ECC/RSA etc.) SCA/DPA/FIA resistant
FortifyIQ’s Crypto Box IP core is a compact, power-efficient cryptographic engine that combines essential asymmetric algorithms (RSA, ECC) with high-s...
276
10.0
Motion JPEG Over IP : HD Video Compression Encoder Subsystem
This Video Over IP Subsystem employs JPEG compression and RTP/UDP/IP encapsulation to enable the rapid development of complete motion JPEG video strea...
277
10.0
Low-power SD/eMMC host controller IP provides advanced high-performance 32- and 64-bit AXI interface to the SoC
The Synopsys SD/eMMC Host Controller IP addresses the growing storage needs of mobile, consumer, IoT and automotive applications. The IP provides adva...
278
10.0
IP Solutions for the AMBA Interconnect
The Synopsys IP solutions for the ARM® AMBA® interconnect include synthesizable IP, verification IP (VIP) and automated assembly with Synopsys’ coreAs...
279
10.0
NR-5G Polar Decoder and Encoder IP Core
The Forward Error Correction (FEC) sub-system is one of the essential basing blocks in any communication systems so a powerful FEC code is needed. The...
280
10.0
ARC EV Processors are fully programmable and configurable IP cores that are optimized for embedded vision applications
Machine vision and deep learning are being embedded in highly integrated SoCs and expanding into high-volume applications such as automotive ADAS, sur...
281
10.0
ARC NPX Neural Processing Unit (NPU) IP supports the latest, most complex neural network models and addresses demands for real-time compute with ultra-low power consumption for AI applications
The new Synopsys ARC NPX Neural Processing Unit (NPU) IP family delivers the industry’s highest performance and support for the latest, most complex n...
282
10.0
Pre-integrated IP blocks with an efficient processor and software in a single subsystem provides a configurable, SoC-ready solution that reduces design and integration effort
As more functionality is integrated into an SoC, it is costly and time consuming to develop and maintain necessary functional blocks that are complex,...
283
10.0
USB 1.1 Digital Controller IP
The Synopsys USB 1.1 Controllers support Full and Low Speed based on USB specification from the USB Implementer Forum. The Synopsys USB 1.1 IP offerin...
284
10.0
USB 2.0 Digital Controller IP
The Synopsys USB 2.0 Controllers support Hi-Speed (480 Mbps), Full Speed (12 Mbps), and Low Speed (1.5 Mbps) operation based on USB specification from...
285
10.0
USB 3.0 Digital Controller IP
The Synopsys SuperSpeed USB IP solution is implemented in hundreds of designs and shipped in millions of units. The USB IP solution is based on the US...
286
10.0
USB 3.1 Controller IP
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offerin...
287
10.0
USB 3.1/DisplayPort 1.3 Controller IP Solutions
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offerin...
288
10.0
USB 3.1/DisplayPort 1.4 IP Subsystem Solution
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offerin...
289
10.0
USB 3.2 Controller IP
The Synopsys SuperSpeed 3.2 USB IP solution is based on the USB 3.2 specification from the USB Implementer Forum. The USB 3.2 IP offering includes con...
290
10.0
USB 3.2 Gen2/Gen1 PHY IP in TSMC(3nm, 5nm, 6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
M31 USB 3.2 Gen2 (support x1/x2) transceiver IP provides a complete range of USB 3.2 Gen2 host and peripheral applications up to 10x2Gbps. It is compl...
291
10.0
TSMC DDR3/4 & LPDDR3/4 Combo IP with AXI and DFI 4.0 Interface
This DDR3/4 and LPDDR3/4 IP combo solution integrates both controller and PHY, designed for TSMC 22nm process. It offers high-performance data rates u...
292
10.0
TSMC DDR3/4 & LPDDR3/4/4x Combo IP with Controller + PHY
This combo IP solution supports DDR3/DDR4 and LPDDR3/LPDDR4/LPDDR4x memory standards, designed for high performance and low power applications on TSMC...
293
10.0
eTCAM (Embedded Ternary Content Addressable Memory IP
TCAM can search for data that matches the input in one cycle from all the information stored in the memory.If there are multiple matching data, it is ...
294
10.0
eTCAM (Embedded Ternary Content Addressable Memory IP
TCAM can search for data that matches the input in one cycle from all the information stored in the memory.If there are multiple matching data, it is ...
295
10.0
Ethernet IPSec/MACSec Switch/Router IP Core - Efficient and Massively Customizable
Packet Architects offers a series of high speed switching/routing IP cores developed using the unique FlexSwitch tool-chain. This allows us to provide...
296
10.0
Ethernet Switch / Router IP Core - Efficient and Massively Customizable
Packet Architects offers a series of high speed switching/routing IP cores developed using the unique FlexSwitch tool-chain. This allows us to provide...
297
10.0
Ethernet TSN Switch IP Core - Efficient and Massively Customizable
Packet Architects offers a series of high speed switching/routing IP cores developed using the unique FlexSwitch tool-chain. This allows us to provide...
298
10.0
Multi Protocol Endpoint IP Core for Safe and Secure Ethernet Network
"The CetraC EndSystem IP coreis the ideal solution to link your Avionic Computer System to a safe & secure embedded network as ARINC664p7, TSN or Safe...
299
10.0
Multi Protocol IO Concentrator (RDC) IP Core for Safe and Secure Ethernet Network
Our IP Core is the ideal solution to link all your equipment, sensor or actuator whatever the used protocol to an Avionic network in a safe & secure m...
300
10.0
Automotive MIPI A-PHY Sink IP (2-Lane)
The CL12912IP4000 is based on MIPI A-PHY interface specification announced in year 2020, targeting ultra-high-speed networking applications in ADAS an...