Silicon Library Inc. IP Cores

You must be registered with the D&R website to view the full search results, including:

Complete datasheets for Silicon Library Inc. IP Core products
Contact information for Silicon Library Inc. IP Core suppliers

Please log in here to your account.

New user ? Signup here.

3151

1.0

TSMC CLN28LP 28nm Deskew PLL - 80MHz-400MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3152

1.0

TSMC CLN28LP 28nm General Purpose PLL - 160MHz-800MHz

The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

3153

1.0

TSMC CLN28LP 28nm Multi Phase DLL - 160MHz-800MHz

The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

3154

1.0

TSMC CLN28LP 28nm Multi Phase DLL - 320MHz-1600MHz

The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

3155

1.0

TSMC CLN28LP 28nm Multi Phase DLL - 80MHz-400MHz

The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

3156

1.0

TSMC CLN28LP 28nm Spread Spectrum PLL - 140MHz-700MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

3157

1.0

TSMC CLN28LP 28nm Spread Spectrum PLL - 280MHz-1400MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

3158

1.0

TSMC CLN28LP 28nm Spread Spectrum PLL - 70MHz-350MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

3159

1.0

TSMC CLN40G 40nm Clock Generator PLL - 170MHz-850MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

3160

1.0

TSMC CLN40G 40nm Clock Generator PLL - 340MHz-1700MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

3161

1.0

TSMC CLN40G 40nm Clock Generator PLL - 680MHz-3400MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

3162

1.0

TSMC CLN40G 40nm DDR DLL - 150MHz-750MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

3163

1.0

TSMC CLN40G 40nm DDR DLL - 200MHz-1000MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

3164

1.0

TSMC CLN40G 40nm DDR DLL - 316MHz-1580MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

3165

1.0

TSMC CLN40G 40nm Deskew PLL - 170MHz-850MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3166

1.0

TSMC CLN40G 40nm Deskew PLL - 340MHz-1700MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3167

1.0

TSMC CLN40G 40nm Deskew PLL - 680MHz-3400MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3168

1.0

TSMC CLN40G 40nm General Purpose PLL - 340MHz-1700MHz

The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

3169

1.0

TSMC CLN40G 40nm Multi Phase DLL - 170MHz-850MHz

The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

3170

1.0

TSMC CLN40G 40nm Multi Phase DLL - 340MHz-1700MHz

The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

3171

1.0

TSMC CLN40G 40nm Multi Phase DLL - 680MHz-3400MHz

The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

3172

1.0

TSMC CLN40G 40nm Spread Spectrum PLL - 150MHz-750MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

3173

1.0

TSMC CLN40G 40nm Spread Spectrum PLL - 300MHz-1500MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

3174

1.0

TSMC CLN40G 40nm Spread Spectrum PLL - 600MHz-3000MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

3175

1.0

TSMC CLN40LP 40nm Clock Generator PLL - 150MHz-750MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

3176

1.0

TSMC CLN40LP 40nm Clock Generator PLL - 300MHz-1500MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

3177

1.0

TSMC CLN40LP 40nm Clock Generator PLL - 75MHz-375MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

3178

1.0

TSMC CLN40LP 40nm DDR DLL - 112MHz-560MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

3179

1.0

TSMC CLN40LP 40nm DDR DLL - 177MHz-885MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

3180

1.0

TSMC CLN40LP 40nm DDR DLL - 84MHz-420MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

3181

1.0

TSMC CLN40LP 40nm Deskew PLL - 150MHz-750MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3182

1.0

TSMC CLN40LP 40nm Deskew PLL - 300MHz-1500MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3183

1.0

TSMC CLN40LP 40nm Deskew PLL - 75MHz-375MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3184

1.0

TSMC CLN40LP 40nm General Purpose PLL - 150MHz-750MHz

The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

3185

1.0

TSMC CLN40LP 40nm Multi Phase DLL - 150MHz-750MHz

The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

3186

1.0

TSMC CLN40LP 40nm Multi Phase DLL - 300MHz-1500MHz

The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

3187

1.0

TSMC CLN40LP 40nm Multi Phase DLL - 75MHz-375MHz

The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

3188

1.0

TSMC CLN40LP 40nm Spread Spectrum PLL - 150MHz-750MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

3189

1.0

TSMC CLN40LP 40nm Spread Spectrum PLL - 300MHz-1500MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

3190

1.0

TSMC CLN40LP 40nm Spread Spectrum PLL - 75MHz-375MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

3191

1.0

TSMC CLN55GP 55nm Clock Generator PLL - 130MHz-650MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

3192

1.0

TSMC CLN55GP 55nm Clock Generator PLL - 260MHz-1300MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

3193

1.0

TSMC CLN55GP 55nm Clock Generator PLL - 520MHz-2600MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

3194

1.0

TSMC CLN55GP 55nm DDR DLL - 150MHz-750MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

3195

1.0

TSMC CLN55GP 55nm DDR DLL - 200MHz-1000MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

3196

1.0

TSMC CLN55GP 55nm DDR DLL - 316MHz-1580MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

3197

1.0

TSMC CLN55GP 55nm Deskew PLL - 130MHz-650MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3198

1.0

TSMC CLN55GP 55nm Deskew PLL - 260MHz-1300MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3199

1.0

TSMC CLN55GP 55nm Deskew PLL - 520MHz-2600MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

3200

1.0

TSMC CLN55GP 55nm General Purpose PLL - 260MHz-1300MHz

The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

65|

66|

...|