Design & Reuse
5757 IP
5751
0.0
Synopsys Verification IP for DDR4 (UDIMM, RDIMM, LDIMM)
Synopsys® VC VerificationIP for the JEDEC DDR4 memory protocol specification provides a comprehensive set of protocol, methodology, verification and p...
5752
0.0
Synopsys Verification IP for LPDDR2
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5753
0.0
Synopsys Verification IP for LPDDR2
Synopsys® VC Verification IP for the JEDEC LPDDR2 memory protocol specification provides a comprehensive set of protocol, methodology, verification an...
5754
0.0
Synopsys Verification IP for LPDDR3
Synopsys® VC VerificationIP for the JEDEC LPDDR3 memory protocol specification provides a comprehensive set of protocol, methodology, verification and...
5755
0.0
Synopsys Verification IP for LPDDR4
Synopsys® VC Verification IP for the JEDEC LPDDR4 memory protocol specification provides a comprehensive set of protocol, methodology, verification an...
5756
0.0
Synopsys Verification IP for UniPro
Synopsys® VC Verification IP for the MIPI Alliance UniPro protocol specification provides a comprehensive set of protocol, methodology, verification a...
5757
0.0
Synthesizable 3DIO IP for Flexible Physical Implementation
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...