Design & Reuse
5757 IP
3851
0.0
GF L55LPX 55nm Ultra PLL - 15MHz-3000MHz
The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, featu...
3852
0.0
GF L65G 65nm Multi Phase DLL - 180MHz-900MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
3853
0.0
GF L65G 65nm Multi Phase DLL - 360MHz-1800MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
3854
0.0
GF L65G 65nm Multi Phase DLL - 90MHz-450MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
3855
0.0
GF L65G 65nm Ultra PLL - 15MHz-3000MHz
The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, featu...
3856
0.0
GF L65LP 65nm IoT PLL - 30MHz-400MHz
The IoT PLL is designed for very low power, sipping only 45uW at 30MHz and running from core power. It has a wide frequency range with multiplication ...
3857
0.0
GF L65LP 65nm Multi Phase DLL - 160MHz-800MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
3858
0.0
GF L65LP 65nm Multi Phase DLL - 320MHz-1600MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
3859
0.0
GF L65LP 65nm Multi Phase DLL - 80MHz-400MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
3860
0.0
GF L65LP 65nm Ultra PLL - 15MHz-3000MHz
The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, featu...
3861
0.0
GF L65LPE 65nm IoT PLL - 30MHz-300MHz
The IoT PLL is designed for very low power, sipping only 45uW at 30MHz and running from core power. It has a wide frequency range with multiplication ...
3862
0.0
GF L65LPE 65nm Multi Phase DLL - 120MHz-600MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
3863
0.0
GF L65LPE 65nm Multi Phase DLL - 240MHz-1200MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
3864
0.0
GF L65LPE 65nm Multi Phase DLL - 60MHz-300MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
3865
0.0
GF L65LPE 65nm Ultra PLL - 15MHz-3000MHz
The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, featu...
3866
0.0
GF L90G 90nm Multi Phase DLL - 120MHz-600MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
3867
0.0
GF L90G 90nm Multi Phase DLL - 240MHz-1200MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
3868
0.0
GF L90G 90nm Multi Phase DLL - 60MHz-300MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
3869
0.0
GF L90GOD 90nm Multi Phase DLL - 180MHz-900MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
3870
0.0
GF L90GOD 90nm Multi Phase DLL - 360MHz-1800MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
3871
0.0
GF L90GOD 90nm Multi Phase DLL - 90MHz-450MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
3872
0.0
GF L90LP 90nm IoT PLL - 30MHz-375MHz
The IoT PLL is designed for very low power, sipping only 45uW at 30MHz and running from core power. It has a wide frequency range with multiplication ...
3873
0.0
GF L90LP 90nm Multi Phase DLL - 150MHz-750MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
3874
0.0
GF L90LP 90nm Multi Phase DLL - 300MHz-1500MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
3875
0.0
GF L90LP 90nm Multi Phase DLL - 75MHz-375MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
3876
0.0
EFFICIERA - Ultra low power AI inference accelerator
LeapMind is currently developing Efficiera , an AI inference accelerator IP with ultra low power consumption, optimized for CNN inference processing ...
3877
0.0
UFS 3.1 Host Controller compatible with M-PHY 4.1 and UniPro 1.8
The Arasan UFS Host -UniPro IP is a simple, high performance, serial interface used primarily in mobile systems between host processing and NVM mass s...
3878
0.0
RGB to CCIR 601 / 656 Encoder
The Digital Blocks DB1892AXI RGB to CCIR 601 / CCIR 656 Encoder interfaces RGB data along with synchronization signals from a LCD Controller such as D...
3879
0.0
RGB to CCIR601/656 Encoder
The Digital Blocks DB1892AXI RGB to CCIR 601 / CCIR 656 Encoder interfaces RGB data along with synchronization signals from a LCD Controller (or any L...
3880
0.0
5GHz to 13.5GHz Phase Locked Loop (PLL) IP Block TSMC 130nm
The PLL13G is a ultra-low power phase locked loop (PLL) intellectual property (IP) block. It features a very small area footprint, with exception...
3881
0.0
Agile ECC/RSA Public Key Accelerator with 128-bit ALU
The impending development of sufficiently powerful quantum computers will break all ECC and RSA public key cryptographic schemes that are deployed in ...
3882
0.0
Agile ECC/RSA Public Key Accelerator with 32-bit ALU
The impending development of sufficiently powerful quantum computers will break all ECC and RSA public key cryptographic schemes that are deployed in ...
3883
0.0
Agile Post Quantum Crypto (PQC) Public Key Accelerator - NIST algorithms
The impending development of sufficiently powerful quantum computers will break all ECC and RSA public key cryptographic schemes that are deployed in ...
3884
0.0
Agile Public Key Accelerator Firmware - RSA, ECC, PQC (ML-KEM, ML-DSA, XMSS, LMS, SLH-DSA)
The impending development of sufficiently powerful quantum computers will break all ECC and RSA public key cryptographic schemes that are deployed in ...
3885
0.0
Agile Public Key Accelerator Host Driver - RSA, ECC, PQC (ML-KEM, ML-DSA, XMSS, LMS, SLH-DSA)
The impending development of sufficiently powerful quantum computers will break all ECC and RSA public key cryptographic schemes that are deployed in ...
3886
0.0
SHA-1 Hashing Core
The ES1002 hash core fully implements the SHA-1 (Secure Hash Algorithm RFC 3174). The core can be used for data authentication in digital broadband, w...
3887
0.0
SHA-3 Secure Hash Crypto Engine
It is compliant with NIST's FIPS 202 standards. The core can provide all the fixed-length hashing functions provided as part of the SHA-3 standard...
3888
0.0
ChaCha20 Crypto Accelerator
The EIP-13 ChaCha engine implements the ChaCha20 algorithm, as specified by [ChaCha]. The accelerators include I/O registers and an encryption/decrypt...
3889
0.0
ChaCha20 DPA Resistant Crypto Accelerator
Rambus DPA Resistant Hardware Cores prevent against the leakage of secret cryptographic key material through attacks when integrated into an SoC or FP...
3890
0.0
AHB 4 Channel DMA Controller
The DMA is a multiple-channel direct memory access controller. The DMA IP Core is a Verilog HDL design that can be used in ASIC, Structured ASIC and F...
3891
0.0
AHB AES with DMA
The Advanced Encryption Standard (AES) IP Core is a complete hardware implementation encryption/decryption algorithm described in the U.S. Government ...
3892
0.0
AHB Arbiter
The AHB Arbiter arbitrates for the AHB bus among as many as four AHB masters. The AHB Arbiter implements a round-robin arbitration algorithm to AHB M...
3893
0.0
AHB Channel with Decoder and Data Mux
The AHB Channel provides the necessary infrastructure to connect as many as 7 AHB Slaves (numbered 1-7) to an AHB bus Master. The AHB Channel perform...
3894
0.0
AHB External Bus Interface
The AHB External Bus Interface (EBI) allows a CPU or AHB Master (such as a DMA core) to transmit and receive data to an external device such as an ext...
3895
0.0
AHB Lite to AXI Bridge
The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction. It is expected that the AXI clock and the...
3896
0.0
AHB Low Power Subsystem - ARM Cortex M0
The AHB Low Power Subsystem is an AMBA® based system that is useful as the basic digital infrastructure for building low power SOCs. The subsystem co...
3897
0.0
AHB Multilayer Interconnect
The AHB-MLIC is a multi-layer AMBA® AHB bus fabric connecting an arbitrary number of bus masters to an arbitrary number of slaves. The multilayer fa...
3898
0.0
AHB Parallel Flash Controller
The AHB Parallel Flash Controller allows an AHB Master (usually a CPU) to read, program, or erase the connected arrangement of external parallel Super...
3899
0.0
AHB Performance Subsystem - ARM Cortex M0
The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs needing additional per...
3900
0.0
AHB Performance Subsystem - ARM Cortex M3
The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs needing additional per...