Design & Reuse
Catalog of SIP Cores
System on Chip design resources
4921 IP
1401
11.0
NVM OTP NeoBit in ASMC (350nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
1402
11.0
NVM OTP NeoBit in CANSEMI (180nm, 110nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
1403
11.0
NVM OTP NeoBit in CSMC (350nm, 250nm, 180nm, 160nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
1404
11.0
NVM OTP NeoBit in DBHitek (180nm, 160nm, 130nm, 110nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
1405
11.0
NVM OTP NeoBit in Fujitsu (180nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
1406
11.0
NVM OTP NeoBit in GLOBALFOUNDRIES (350nm, 250nm, 180nm, 160nm, 150nm, 130nm, 110nm, 65nm, 55nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
1407
11.0
NVM OTP NeoBit in Grace (180nm, 160nm, 130nm, 110nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
1408
11.0
NVM OTP NeoBit in GTA (150nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
1409
11.0
NVM OTP NeoBit in HJTC (180nm, 160nm, 110nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
1410
11.0
NVM OTP NeoBit in Huali (55nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
1411
11.0
NVM OTP NeoBit in JSC (130nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
1412
11.0
NVM OTP NeoBit in MagnaChip (350nm, 180nm, 150nm, 130nm, 110nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
1413
11.0
NVM OTP NeoBit in Maxchip (180nm, 160nm, 150nm, 110nm, 90nm, 80nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
1414
11.0
NVM OTP NeoBit in NEXCHIP (150nm, 110nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
1415
11.0
NVM OTP NeoBit in Samsung (130nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
1416
11.0
NVM OTP NeoBit in SHARP (180nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
1417
11.0
NVM OTP NeoBit in Silterra (180nm, 160nm, 130nm, 110nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
1418
11.0
NVM OTP NeoBit in SKHYNIX (180nm, 130nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
1419
11.0
NVM OTP NeoBit in SMIC (350nm, 180nm, 160nm, 130nm, 110nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
1420
11.0
NVM OTP NeoBit in TSMC (350nm, 250nm, 180nm, 160nm, 130nm, 110nm, 90nm, 80nm, 55nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
1421
11.0
NVM OTP NeoBit in UMC (180nm, 160nm, 130nm, 110nm, 80nm, 55nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
1422
11.0
NVM OTP NeoBit in Vanguard (350nm, 250nm, 180nm, 160nm, 150nm, 110nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
1423
11.0
NVM OTP NeoBit in X-FAB (250nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
1424
10.0
4-/8-bit mixed-precision NPU IP
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
1425
10.0
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY...
1426
10.0
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY...
1427
10.0
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY...
1428
10.0
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY...
1429
10.0
HBM3 PHY IP at 7nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
1430
10.0
GDDR6 Memory Controller IP
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
1431
10.0
GDDR6 PHY IP for 12nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
1432
10.0
Gigabit Ethernet PHY
Gigabit Ethernet PHY...
1433
10.0
Gigabit Ethernet PHY
Gigabit Ethernet PHY (in production)...
1434
10.0
Gigabit Ethernet PHY
Gigabit Ethernet PHY...
1435
10.0
Gigabit Ethernet PHY
Gigabit Ethernet PHY...
1436
10.0
Gigabit Ethernet PHY (Modification Right)
Gigabit Ethernet PHY Modification Right (in production)...
1437
10.0
Highly scalable inference NPU IP for next-gen AI applications
OPENEDGES, the total memory subsystem IP provider, introduces ENLIGHT Pro, a state-of-the-art inference neural processing unit (NPU) IP that outperfor...
1438
10.0
RISC-V Vector Unit
A Vector Unit is composed of several 'vector cores', roughly equivalent to a GPU core, that perform multiple calculations in parallel. Each vector cor...
1439
10.0
OneStar Technology Engineering Services
OneStar Technology is a professional Silicon Intellectual Property (SIP) solution provider, while also offers Electronic Design Automation (EDA), Comp...
1440
10.0
UniPro 1.6 Host/Device IP
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
1441
10.0
UniPro 1.8 Host/Device IP
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
1442
10.0
UniPro 1.8 Host/Device IP
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
1443
10.0
UniPro Controller 2.0 IP (host / device)
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
1444
10.0
USB 3.2 Gen2/Gen1 PHY IP in TSMC(3nm, 5nm, 6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
M31 USB 3.2 Gen2 (support x1/x2) transceiver IP provides a complete range of USB 3.2 Gen2 host and peripheral applications up to 10x2Gbps. It is compl...
1445
6.0
Technology Development Services
CSEM – Pioneering Ultra-Low Power ASIC and SoC Innovation CSEM is a Swiss public-private, non-profit technology innovation center with over 40 year...
1446
5.0
32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP (DSP)
The 32-bit D45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compr...
1447
5.0
32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux
The 32-bit A45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compr...
1448
5.0
32-bit Multiprocessor with Level-2 Cache-Coherence
AndesCore™ A25MP 32-bit multicore CPU IP is based on AndeStar™ V5 architecture. It supports RISC-V standard ‘IMAC-FD’ extensions, Andes contributed DS...
1449
5.0
M31 ADC / Temp. Sensor IP in 12nm, 14nm, 22nm Process
The M31 SAR ADC provides a rich portfolio with a resolution from 10 to 12-bit, maximum speed up to 2.5MSPS, and supports input types of single-ended o...
1450
5.0
M31 Digital PLL IP in 3nm, 5nm, 6nm, 7nm, 12nm, 16nm, 22nm,28nm,40nm
M31 Digital PLL is a core-power only programmable phase-locked loop (PLL) for frequency synthesis. It supports multiple modes of operation for several...