Design & Reuse
4907 IP
1401
11.0
NVM OTP NeoBit in Vanguard (350nm, 250nm, 180nm, 160nm, 150nm, 110nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
1402
11.0
NVM OTP NeoBit in X-FAB (250nm)
eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-mode, analog, Radio-Fr...
1403
10.0
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY...
1404
10.0
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY...
1405
10.0
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY...
1406
10.0
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY...
1407
10.0
HBM3 PHY IP at 7nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
1408
10.0
GDDR6 PHY IP for 12nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
1409
10.0
Gigabit Ethernet PHY
Gigabit Ethernet PHY (in production)...
1410
10.0
Gigabit Ethernet PHY
Gigabit Ethernet PHY...
1411
10.0
Gigabit Ethernet PHY
Gigabit Ethernet PHY...
1412
10.0
Gigabit Ethernet PHY
Gigabit Ethernet PHY...
1413
10.0
Gigabit Ethernet PHY (Modification Right)
Gigabit Ethernet PHY Modification Right (in production)...
1414
10.0
RISC-V Vector Unit
A Vector Unit is composed of several 'vector cores', roughly equivalent to a GPU core, that perform multiple calculations in parallel. Each vector cor...
1415
10.0
OneStar Technology Engineering Services
OneStar Technology is a professional Silicon Intellectual Property (SIP) solution provider, while also offers Electronic Design Automation (EDA), Comp...
1416
10.0
UniPro 1.6 Host/Device IP
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
1417
10.0
UniPro 1.8 Host/Device IP
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
1418
10.0
UniPro 1.8 Host/Device IP
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
1419
10.0
UniPro Controller 2.0 IP (host / device)
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
1420
10.0
USB 3.2 Gen2/Gen1 PHY IP in TSMC(3nm, 5nm, 6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
M31 USB 3.2 Gen2 (support x1/x2) transceiver IP provides a complete range of USB 3.2 Gen2 host and peripheral applications up to 10x2Gbps. It is compl...
1421
6.0
Technology Development Services
CSEM – Pioneering Ultra-Low Power ASIC and SoC Innovation CSEM is a Swiss public-private, non-profit technology innovation center with over 40 year...
1422
5.0
32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP (DSP)
The 32-bit D45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compr...
1423
5.0
32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux
The 32-bit A45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compr...
1424
5.0
32-bit Multiprocessor with Level-2 Cache-Coherence
AndesCore™ A25MP 32-bit multicore CPU IP is based on AndeStar™ V5 architecture. It supports RISC-V standard ‘IMAC-FD’ extensions, Andes contributed DS...
1425
5.0
M31 ADC / Temp. Sensor IP in 12nm, 14nm, 22nm Process
The M31 SAR ADC provides a rich portfolio with a resolution from 10 to 12-bit, maximum speed up to 2.5MSPS, and supports input types of single-ended o...
1426
5.0
M31 Digital PLL IP in 3nm, 5nm, 6nm, 7nm, 12nm, 16nm, 22nm,28nm,40nm
M31 Digital PLL is a core-power only programmable phase-locked loop (PLL) for frequency synthesis. It supports multiple modes of operation for several...
1427
5.0
M31 DisplayPort RX IP in 6/7nm, 22nm
M31 DisplayPort RX IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. DisplayPort RX supp...
1428
5.0
M31 eUSB2 PHY IP(2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 28nm)
Embedded USB2 (eUSB2) is a new generation specification proposed by USB Association that extends USB 2.0 specification and uses 1.2V/1.0V as the inter...
1429
5.0
64-Bit 8-stage superscalar processor that supports RISC-V specification, including GCN
The 64-bit NX45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit comp...
1430
5.0
64-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux
The 64-bit AX45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit comp...
1431
5.0
64-bit CPU Core with Level-2 Cache Controller
The 64-bit AX27L2 is a 5-stage processor that supports the latest RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit comp...
1432
5.0
64-bit CPU with Modern RISC Architecture, MemBoost and PMA
The 64-bit AX27 is a 5-stage processor that supports the latest RISC-V specification, including "G" ("IMAFD") standard instructions, "C" 16-bit compre...
1433
5.0
64-bit CPU with RISC-V Vector Extension
The 64-bit NX27V is a vector processor with 5-stage scalar pipeline that supports the latest RISC-V specification, including the IMAFD standard instru...
1434
5.0
64-bit CPU with RISC-V Vector Extension
The 64-bit NX27V is a vector processor with 5-stage scalar pipeline that supports the latest RISC-V specification, including the IMAFD standard instru...
1435
5.0
64-bit Multiprocessor with Level-2 Cache-Coherence
AndesCore™ AX25MP 64-bit multicore CPU IP is based on AndeStar™ V5 architecture. It supports RISC-V standard 'IMAC-FD' extensions, Andes contributed D...
1436
5.0
64-bit RISC-V Multicore Processor with 1024-bit Vector Extension
AndesCore™ AX45MPV 64-bit multicore CPU IP is an 8-stage superscalar processor with Vector Processing Unit (VPU) based on AndeStar™ V5 architecture. I...
1437
5.0
DDR4/LPDDR4/LPDDR4X PHY
M31 LPDDR4X multi-PHY supports both LPDDR4 and LPDDR4X memory interfaces at speed up to 4267Mbps, making it an ideal solution for ASICS, ASSPs, SOC an...
1438
5.0
Memory Compiler(12nm,16nm,22nm,28nm,40nm,55nm, 90nm, 115nm, 130nm, 150nm, 180nm)
M31 memory compilers are designed with high industrial standards to which provides the memory solutions for density, power, and performance optimizati...
1439
5.0
General Purpose I/O (GPIO)(12nm,16nm,22nm, 28nm, 40nm, 55nm, 90nm, 110nm, 130nm, 150nm,152nm, 180nm)
GPIO is a general-purpose input/output unit that provides basic input/output functionalities. M31 provides silicon-proven GPIO libraries in a variety ...
1440
5.0
Efficient 32-bit Processor with Custom Instructions
The new Andes Technology E8 CPU processor core targets Internet of Things (IoT) applications with the unique Andes Custom Extension™ (ACE) on a power-...
1441
5.0
High-efficiency Low-power Processor
System-on-chip designs are proliferating to help OEMs automate functions such as smart lights, heating and cooling, wireless door locks, smoke, fire, ...
1442
5.0
High-performance Processor for Real-time and Linux Applications
The Andes Technology N13 processor is a high performance CPU core architected for computation intensive applications running either on operating syste...
1443
5.0
Highly-Configurable 32-bit Processor
The AndesCore N9 Family is intended for deeply embedded applications that require optimal interrupt response features, including wireless networking a...
1444
5.0
MIPI C-PHY v2.0 /D-PHY v2.5 Combo IP
MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices. To further improve thr...
1445
5.0
MIPI C-PHY v2.0 /D-PHY v2.5 Combo IP
MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices. To further improve thr...
1446
5.0
RISC-V CPU IP With ISO 26262 Full Compliance
AndesCore™ N25F is a 32-bit CPU IP core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it is capable of delivering high per-...
1447
5.0
DisplayPort TX IP for high-bandwidth applications (6nm, 12nm, 28nm)
M31 DisplayPort TX IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. DisplayPort TX supp...
1448
5.0
Ultra Compact 32-bit RISC-V CPU Core
AndesCore™ N22 is a 32-bit 2-stage pipeline CPU IP core based on AndeStar™ V5 architecture for embedded applications that require low energy consumpti...
1449
5.0
Integrated ESD cell designs for General I/O, eMMC I/Os, SDIOs, and ONFI I/O(12nm~180nm)
M31’s I/O Libraries now include integrated ESD cell designs for General I/O, eMMC I/Os, SDIOs, and ONFI I/O. We provide standard JEDEC ESD level and c...
1450
5.0
Entry-level Low-Power 32-bit Processor
N705 is an ultra low-power small-size synthesizable general purpose 32-bit softcore embedded processor. With competitive small core size, high power-e...