Design & Reuse
4907 IP
201
3.0
Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 28HPC process
TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
202
3.0
Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 55LP process
TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
203
3.0
Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 65GP process
TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
204
3.0
Single Lane and Quad Lane 16Gbps PCIe4.0 PHY IP in TSMC 28HPC process
TERMINUS CIRCUITS PCIe GEN4.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
205
3.0
Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in GF 28SLP process
TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol a...
206
3.0
Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 28HPC process
TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
207
3.0
Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 55LP process
TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
208
3.0
Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 65GP process
TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
209
3.0
Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in GF 28SLP process
TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
210
3.0
Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 28HPC process
TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
211
3.0
Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 55LP process
TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
212
3.0
Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 65GP process
TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
213
3.0
Single Lane and Quad Lane 8Gbps PCIe3.0 PHY in Samsung 28LPP process
TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
214
3.0
Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in GF 28SLP process
TERMINUS-CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single &Quad-Lane PCI Express PHY that supports PCI Express protocol and...
215
3.0
Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in TSMC 28HPC process
TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
216
3.0
Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in TSMC 65G process
TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
217
3.0
MIPI 4.1 M-PHY HS Gear 4
MIPI M-PHY HS Gear 4 IP is compliant with the MIPI serial communication protocol for use in mobile systems where performance, power, and efficiency ar...
218
3.0
MIPI PHY
This MIPI D-PHY IP is designed to compliant with the MIPI D-PHY v1.2 specifications. It is designed for low power and high-performance application. Th...
219
3.0
Low Jitter 1.25GHz to 2.5GHz Quadrature Output PLL
Terminus Circuits offers High speed, low Jitter PLL with 1.25GHz to 2.5GHz output. The ring oscillator based PLL provides balanced quadrature output. ...
220
3.0
LPDDR2/3/4/4x IP combo solution with high performance and low power
With sophisticated architecture and advanced technology, this LPDDR2/3/4/4x IP combo solution with high performance and low power. In 12~28nm CMOS pro...
221
3.0
USB 2.0 (LS, FS & HS) On-The-Go IP Core
A 'Dual-Role' USB On-The-Go IP Core that operates as both an USB peripheral or as an USB OTG host in a point-to-point communications with another USB ...
222
3.0
Multi-Link Multi-Protocol SerDes 10Gbps in GF 28SLP
Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SA...
223
3.0
Multi-Link Multi-Protocol SerDes 10Gbps in TSMC 55LP
Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SA...
224
3.0
Multi-Link Multi-Protocol SerDes 10Gbps in TSMC 65GP
Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SA...
225
3.0
Multi-Link Multi-Protocol SerDes 16Gbps in TSMC 28HPC
Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SA...
226
2.0
56G SerDes Ethernet
56G SerDes IP core supports PAM4 signaling in the range of 25.0-60.0 Gbps using full-rate and half-rate modes with scrambled data. Non-return-to-zero ...
227
1.0
2.5V 12Bit pipeline analog to digital converter
TheS65LLV25_ADC_13 IP is a 2.5V 12Bit pipeline analog to digital converter capable of running at up to 100MHz conversion rate with 2Vp-p input range....
228
1.0
S13_DAC_03 CMOS 10-BIT 200MSPS+CURRENT-STEERING D/A Converter
The S13_DAC_03 is a 10-bit resolution, high performance, low power, current-steering CMOS digital-to-analog converter (DAC). The input update rate can...
229
1.0
12-bit 1M Differential Rail to Rail SAR ADC
The analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution. The ADC includes a core intern...
230
1.0
12-bit 8 Input 1M/200k SAR ADC)
This analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution. The IP includes a core intern...
231
1.0
12-Bit SAR ADC in GlobalFoundries 22nm FDSOI
This analog-to-digital converter (ADC) uses successive approximation register (SAR) architecture to achieve 12-bit resolution. The ADC includes intern...
232
1.0
12-Bit SAR ADC in GlobalFoundries 22nm FDSOI
This analog-to-digital converter (ADC) uses successive approximation register (SAR) architecture to achieve 12-bit resolution. The ADC includes intern...
233
1.0
32:1 serializer followed by sub-LVDS drivers
The CCP2 transmitter consists of a 32:1 serializer followed by LVDS drivers for transmitting clock (or strobe) and data. The LVDS drivers operate in s...
234
1.0
I2C Master and Slave
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable for app...
235
1.0
650M LVDS transmitter, 5 channel
The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolution and Dual Link tra...
236
1.0
Samsung 28nm FDSOI 1.8v/1.0v APLL
...
237
1.0
Samsung 28nm FDSOI 1.8v/1.0v APLL
This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 800MHz to 3200MHz. By setting DM [3:0] ...
238
1.0
Samsung 28nm FDSOI 1.8v/1.0v LVDS Transmitter
...
239
1.0
Samsung 28nm FDSOI 1.8v/1.0v sub-LVDS Receiver
...
240
1.0
Samsung 28nm FDSOI Codec
The SEC28FDSOI18_CODEC_04 integrates: 2-channel 24-bit sigma-delta ADC, 2-channel 24-bit sigma-delta DAC with headphone driver amplifier, and audio PL...
241
1.0
Samsung 28nm FDSOI MIPI DPHY V1.1
...
242
1.0
SAMSUNG 28nm FDSOI USB2.0 Dual Role PHY/OTG PHY
The USB 2.0 OTG PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard. It provides a High/Full-Speed USB analog fro...
243
1.0
Samsung 28nm FDSOI USB3.0 and PCIE2 combo PHY
The USB3.0 Super-Speed / PCI Express Combo PHY is a programmable IP that is compatible with the PHY Interface for PCI Express and USB3.0 Super-Speed A...
244
1.0
Samsung 28nm FDSOI USB3.0 Type-C PHY
...
245
1.0
Samsung 28nm Low Power Single-Port SRAM Compiler
VeriSilicon Samsung 28FDSOI Low Power Synchronous Single-Port SRAM compiler optimized for Samsung FDSOI 28nm process can flexibly generate memory bloc...
246
1.0
Samsung 28nm Low Voltage Single-Port SRAM Compiler
VeriSilicon Samsung 28FDSOI Low Voltage Synchronous Single-Port SRAM compiler optimized for Samsung FDSOI 28nm process can flexibly generate memory bl...
247
1.0
IBM 10SF 65nm 2.5v PLL
Designed for audio clock generation, this PLL integrates a phase frequency detector (PFD), a loop filter (LP), a voltage control oscillator (VCO), a c...
248
1.0
IBM 10SF 65nm 2.5v PLL
This PLL is designed for audio clock generation. The reference clock is 12MHz, 13.5MHz or 19.2MHz, which can be either from crystal OSC or from intern...
249
1.0
IBM 65nm 1.0/2.5V 32768Hz Crystal Oscillator
This is a 32768Hz crystal oscillator specifically designed for ultra-low power application. The sole power supply is 3.3V, but it can be as low as 1.6...
250
1.0
IBM 65nm 10SF Process 24-Bit Stereo Sigma-Delta ADC/DAC
The I65GV25_CODEC_04 integrates: 2-channel 24-bit sigma-delta ADC, 2-channel 24-bit sigma-delta DAC with headphone driver amplifier, and audio PLL to ...